Datasheet

Data Sheet AD9559
Rev. C | Page 103 of 120
Table 152. IRQ Clearing for Reference Inputs
Address Bits Bit Name Description
0x0A07 7 Reserved Reserved
6
REFB validated
Clears IRQ indicating that REFB has been validated
5 REFB fault cleared Clears IRQ indicating that REFB has been cleared of a previous fault
4 REFB fault Clears IRQ indicating that REFB has been faulted
3 Reserved Reserved
2 REFA validated Clears IRQ indicating that REFA has been validated
1 REFA fault cleared Clears IRQ indicating that REFA has been cleared of a previous fault
0 REFA fault Clears IRQ indicating that REFA has been faulted
0x0A08 7 Reserved Reserved
6 REFD validated Clears IRQ indicating that REFD has been validated
5 REFD fault cleared Clears IRQ indicating that REFD has been cleared of a previous fault
4
REFD fault
Clears IRQ indicating that REFD has been faulted
3 Reserved Reserved
2 REFC validated Clears IRQ indicating that REFC has been validated
1 REFC fault cleared Clears IRQ indicating that REFC has been cleared of a previous fault
0 REFC fault Clears IRQ indicating that REFC has been faulted
Table 153. IRQ Clearing for Digital PLL0 (DPLL_0)
Address Bits Bit Name Description
0x0A09 7 Frequency unclamped Clears IRQ indicating that DPLL_0 has exited a frequency clamped state
6 Frequency clamped Clears IRQ indicating that DPLL_0 has entered a frequency clamped state
5
Phase slew unlimited
Clears IRQ indicating that DPLL_0 has exited a phase slew limited state
4 Phase slew limited Clears IRQ indicating that DPLL_0 has entered a phase slew limited state
3 Frequency unlocked Clears IRQ indicating that DPLL_0 has lost frequency lock
2 Frequency locked Clears IRQ indicating that DPLL_0 has acquired frequency lock
1 Phase unlocked Clears IRQ indicating that DPLL_0 has lost phase lock
0 Phase locked Clears IRQ indicating that DPLL_0 has acquired phase lock
0x0A0A 7 DPLL_0 switching Clears IRQ indicating that DPLL_0 is switching to a new reference
6 DPLL_0 free run Clears IRQ indicating that DPLL_0 has entered free run mode
5 DPLL_0 holdover Clears IRQ indicating that DPLL_0 has entered holdover mode
4 History updated Clears IRQ indicating that DPLL_0 has updated its tuning word history
3
REFD activated
Clears IRQ indicating that DPLL_0 has activated REFD
2 REFC activated Clears IRQ indicating that DPLL_0 has activated REFC
1 REFB activated Clears IRQ indicating that DPLL_0 has activated REFB
0 REFA activated Clears IRQ indicating that DPLL_0 has activated REFA
0x0A0B [7:5] Reserved Reserved
4 Sync distribution Clears IRQ indicating a distribution sync event
3 APLL_0 unlocked Clears IRQ indicating that APLL_0 has been unlocked
2 APLL_0 locked Clears IRQ indicating that APLL_0 has been locked
1 APLL_0 cal complete Clears IRQ indicating that APLL_0 calibration complete
0 APLL_0 cal started Clears IRQ indicating that APLL_0 calibration started