Datasheet

AD9559 Data Sheet
Rev. C | Page 10 of 120
TIME DURATION OF DIGITAL FUNCTIONS
Table 9.
Parameter Min Typ Max Unit Test Conditions/Comments
TIME DURATION OF DIGITAL FUNCTIONS
EEPROM-to-Register Download Time
16
25
ms
Uses default EEPROM storage sequence (see Register 0x0E10
to Register 0x0E4F)
Register-to-EEPROM Upload Time 180 ms Uses default EEPROM storage sequence (see Register 0x0E10
to Register 0x0E4F
Power-Down Exit Time
1
ms Time from power-down exit to system clock lock detect; system
clock stability timer setting should be added to calculate the
time needed for system clock stable
DIGITAL PLL (DPLL_0 AND DPLL_1)
Table 10.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL PLL
Phase Frequency Detector (PFD) Input
Frequency Range
2 100 kHz
Loop Bandwidth 0.1 2000 Hz Programmable design parameter;
note that (f
PFD
/loop BW) ≥ 20
Phase Margin 45 89 Degrees Programmable design parameter
Closed Loop Peaking
<0.1
dB
Programmable design parameter; part can be programmed
for <0.1 dB peaking in accordance with Telcordia GR-253-CORE
jitter transfer
ANALOG PLL (APLL_0 AND APLL_1)
Table 11.
Parameter Min Typ Max Unit Test Conditions/Comments
ANALOG PLL0
VCO Frequency Range 2940 3543 MHz
Phase Frequency Detector (PFD) Input
Frequency Range
180
195
MHz
Loop Bandwidth 240 kHz Programmable design parameter
Phase Margin 68 Degrees Programmable design parameter
ANALOG PLL1
VCO Frequency Range 3405 4260 MHz
Phase Frequency Detector (PFD) Input
Frequency Range
180 195 MHz
Loop Bandwidth 240 kHz Programmable design parameter
Phase Margin 68 Degrees Programmable design parameter
DIGITAL PLL LOCK DETECTION
Table 12.
Parameter Min Typ Max Unit Test Conditions/Comments
PHASE LOCK DETECTOR
Threshold Programming Range 10 2
24
− 1 ps Reference-to-feedback phase difference
Threshold Resolution 1 ps
FREQUENCY LOCK DETECTOR
Threshold Programming Range 10 2
24
− 1 ps Reference-to-feedback period difference
Threshold Resolution 1 ps
HOLDOVER SPECIFICATIONS
Table 13.
Parameter Min Typ Max Unit Test Conditions/Comments
HOLDOVER SPECIFICATIONS
Initial Frequency Accuracy <0.01 ppm Excludes frequency drift of SYSCLK source; excludes frequency
drift of input reference prior to entering holdover; compliant
with GR-1244 Stratum 3