Datasheet

AD9558 Data Sheet
Rev. B | Page 94 of 104
Table 102. SYSCLK Status
Address Bits Bit Name Description
0x0D01 7 Reserved Reserved.
6
DPLL_APLL_Lock
Indicates the status of the DPLL and APLL.
0 = either the DPLL or the APLL is unlocked.
1 = both the DPLL and APLL are locked.
5
All PLLs locked
Indicates the status of the system clock PLL, APLL, and DPLL.
0 = system clock PLL or APLL or DPLL is unlocked.
1 = all three PLLs (system clock PLL, APLL, and DPLL) are locked.
4
APLL VCO status
1 = OK.
0 = off/clocks are missing.
3
APLL cal in process
The control logic holds this bit set while the amplitude calibration of the APLL VCO is in progress.
2 APLL lock
Indicates the status of the APLL.
0 = unlocked.
1 = locked.
1
System clock stable
The control logic sets this bit when the device considers the system clock to be stable (see
the System Clock Stability Timer section).
0 = not stable (the system clock stability timer has not expired yet).
1 = stable (the system clock stability timer has expired).
0
SYSCLK lock detect
Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked.
IRQ Monitor (Register 0x0D02 to Register 0x0D09)
If not masked via the IRQ mask registers (Register 0x0209 to Register 0x020F), the appropriate IRQ monitor bit is set to a Logic 1 when
the indicated event occurs. These bits can be cleared only via the IRQ clearing registers (Register 0x0A04 to Register 0x0A09), the reset all
IRQs bit (Register 0x0A03[1]), or a device reset.
Table 103. IRQ Monitor for SYSCLK
Address Bits Bit Name Description
0x0D02 [7:6] Reserved Reserved
5
SYSCLK unlocked Indicates a SYSCLK PLL state transition from locked to unlocked
4
SYSCLK locked Indicates a SYSCLK PLL state transition from unlocked to locked
3
APLL unlocked Indicates an output PLL state transition from locked to unlocked
2
APLL locked Indicates an output PLL state transition from unlocked to locked
1
APLL cal ended Indicates that APLL calibration is complete
0
APLL cal started Indicates that APLL in APLL calibration has begun
Table 104. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM
Address Bit Bit Name Description
0x0D03
[7:5] Reserved Reserved
4
Pin program end
Indicates successful completion of a ROM load operation
3 Output distribution sync Indicates a distribution sync event
2
Watchdog timer Indicates expiration of the watchdog timer
1
EEPROM fault Indicates a fault during an EEPROM load or save operation
0
EEPROM complete Indicates successful completion of an EEPROM load or save operation