Datasheet

AD9558 Data Sheet
Rev. B | Page 88 of 104
Table 83. DPLL Loop BW Scaling Factor—REFA Profile
1
Address Bits Bit Name Description
0x070F
[7:0]
DPLL loop BW scaling factor
(unit of 0.1 Hz)
Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).
0x0710
[7:0]
Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).
The default for Register 0x070F to Register 0x0710 = 0x01F4 = 500 (50 Hz loop bandwidth).
The loop bandwidth should always be less than the DPLL phase detector frequency
divided by 20.
0x0711 [7:1] Reserved Default: 0x00.
0
BW scaling factor Digital PLL loop bandwidth scaling factor, Bit 16 (default: 0b).
1
Note that the default DPLL loop BW is 50.4 Hz.
Table 84. R-Divider—REFA Profile
1
Address Bits Bit Name Description
0x0712
[7:0]
R divider
DPLL integer reference divider (minus 1), Bits[7:0] (default: 0xC5)
0x0713 [7:0] DPLL integer reference divider, Bits[15:8] (default: 0x00)
0x0714
[7:5] Reserved Reserved. Default: 0x0
4
Enable REFA div2
Enables the reference input divide-by-2 for REFA
0 = bypass the divide-by-2 (default)
1 = enable the divide-by-2
[3:0]
R divider
DPLL integer reference divider, Bits[19:16] (default: 0x0).
The default for Register 0x0712 to Register 0x0714 = 0x000C5 = 197 (which equals R = 198).
1
Note that the value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.
Table 85. Integer Part of Fractional Feedback Divider N1—REFA Profile
1
Address Bits Bit Name Description
0x0715
[7:0] Integer Part N1 DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0x6B).
0x0716
[7:0]
DPLL integer feedback divider, Bits[15:8] (default: 0x07).
0x0717 [7:1] Reserved Reserved. Default: 0x00.
0
Integer Part N1 DPLL integer feedback divider, Bit 16 (default: 0b).
The default for Register 0x0715 to Register 0x717 = 0x0076B (which equals N1 = 1900).
1
Note that the value stored in the N1-divider register yields an actual divide ratio of one more than the programmed value.
Table 86. Fractional Part of Fractional Feedback Divider FRAC1—REFA Profile
Address Bits Bit Name Description
0x0718
[7:0]
Digital PLL fractional feedback
divider—FRAC1
The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04)
0x0719
[7:0] The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x071A
[7:0]
The numerator of the fractional-N feedback divider, Bits[23:16] (default: 0x00)
Table 87. Modulus of Fractional Feedback Divider MOD1—REFA Profile
Address Bits Bit Name Description
0x071B
[7:0]
Digital PLL feedback divider
modulus—MOD1
The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05)
0x071C
[7:0] The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x071D
[7:0] The denominator of the fractional-N feedback divider, Bits[23:16] (default: 0x00)
Table 88. Phase and Frequency Lock Detector Controls—REFA Profile
Address Bits Bit Name Description
0x071E
[7:0] Phase lock threshold Phase lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps
0x071F
[7:0] Phase lock threshold, Bits[15:8] (default: 0x02)
0x0720
[7:0]
Phase lock fill rate
Phase lock fill rate, Bits[7:0] (default:0x0A = 10 code/PFD cycle)
0x0721 [7:0] Phase lock drain rate Phase lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
0x0722
[7:0] Frequency lock threshold Frequency lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps
0x0723
[7:0] Frequency lock threshold, Bits[15:8] (default: 0x02)
0x0724
[7:0] Frequency lock threshold, Bits[23:16] (default: 0x00)
0x0725
[7:0] Frequency lock fill rate Frequency lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
0x0726
[7:0] Frequency lock drain rate Frequency lock drain rate bits[7:0] (default: 0x0A = 10 code/PFD cycle)