Datasheet

Data Sheet AD9558
Rev. B | Page 81 of 104
OUTPUT CLOCK DISTRIBUTION (REGISTER 0x0500 TO REGISTER 0x0515)
Table 67. Clock Distribution Output Synchronization Settings
Address Bits Bit Name Description
0x0500
7
Mask Channel 3 sync
Masks the synchronous reset to the Channel 3 (M3) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 3 from the static SYNC state,
thus allowing the Channel 3 divider to toggle. Channel 3 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel. In
addition, the output distribution sync also depends on the setting of Register 0x0405[3].
6 Mask Channel 2 sync Masks the synchronous reset to the Channel 2 (M2) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 2 from the static SYNC state,
thus allowing the Channel 2 divider to toggle. Channel 2 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel. In
addition, the output distribution sync also depends on the setting of Register 0x0405[3].
5 Mask Channel 1 sync Masks the synchronous reset to the Channel 1 (M2) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 1 from the static SYNC state,
thus allowing the Channel 1 divider to toggle. Channel 1 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this
channel. In addition, the output distribution sync also depends on the setting of Register
0x0405[3].
4
Mask Channel 0 sync Masks the synchronous reset to the Channel 0 (M0) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 0 from the static SYNC state,
thus allowing the Channel 0 divider to toggle. Channel 0 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel. In
addition, the output distribution sync also depends on the setting of Register 0x0405[3].
3
Reserved Default: 0b.
2
Sync source selection Selects the sync source for the clock distribution output channels.
0 (default) = direct. The sync pulse happens on the next I/O update.
1 = active reference.
Note that the output distribution sync also depends on the APLL being calibrated and
locked unless Register 0x0405[3] = 1b.
[1:0]
Automatic sync mode Autosync mode.
00 = disabled. A sync command must be issued manually, or by using the mask sync bits
in this register (Bits[7:4]).
01 = sync on DPLL frequency lock.
10 (default) = sync on DPLL phase lock.
11 = reserved.