Datasheet

Data Sheet AD9558
Rev. B | Page 77 of 104
Table 57. Fixed Closed-Loop Phase Lock Offset
Address Bits Bit Name Description
0x030C
[7:0] Fixed phase lock offset (signed; ps)
Fixed phase lock offset, Bits[7:0].
Default: 0x00.
0x030D
[7:0]
Fixed phase lock offset, Bits[15:8].
Default 0x00.
0x030E
[7:0]
Fixed phase lock offset, Bits[23:16].
Default: 0x00.
0x030F
[7:6]
Reserved
Reserved; default: 0x0.
[5:0] Fixed phase lock offset (signed; ps)
Fixed phase lock offset, Bits[29:24].
Default: 0x00.
Table 58. Incremental Closed-Loop Phase Lock Offset Step Size
1
Address Bits Bit Name Description
0x0310
[7:0]
Incremental phase lock offset
step size (ps)
Incremental phase lock offset step size, Bits[7:0].
Default: 0x00.
This controls the static phase offset of the DPLL while it is locked.
0x0311
[7:0]
Incremental phase lock offset step size, Bits[15:8].
Default: 0x00.
This controls the static phase offset of the DPLL while it is locked.
1
Note that the default incremental closed-loop phase lock offset step size value is 0x0000 = 0 (0 ns).
Table 59. Phase Slew Rate Limit
Address Bits Bit Name Description
0x0312
[7:0] Phase slew rate limit (µs/sec)
Phase slew rate limit, Bits[7:0].
Default: 0x00.
This register controls the maximum allowable phase slewing during transients
and reference switching.
The default phase slew rate limit is 0, or disabled. Minimum useful value is 310 µs/sec.
0x0313
[7:0]
Phase slew rate limit, Bits[15:8].
Default: 0x00.
Table 60. History Accumulation Timer
Address Bits Bit Name Description
0x0314
[7:0] History accumulation timer (ms)
History accumulation timer bits[7:0].
Default: 0x0A. For Register 0x0314 and Register 0x0315, 0x000A = 10 ms.
Maximum is 65 sec. This register controls the amount of tuning word averaging used
to determine the tuning word used in holdover. Never program a timer value of
zero. The default value is 0x000A = 10 decimal, which equates to 10 ms
0x0315
[7:0]
History accumulation timer bits[15:8].
Default: 0x00.