Datasheet

Data Sheet AD9558
Rev. B | Page 73 of 104
SYSTEM CLOCK (REGISTER 0x0100 TO REGISTER 0x0108)
Table 42. System Clock PLL Feedback Divider (N3 Divider)
Address Bits Bit Name Description
0x0100
[7:0]
SYSCLK N3 divider
System clock PLL feedback divider value: 4 ≤ N3 ≤ 255 (default: 0x08).
Table 43. SYSCLK Configuration
Address Bits Bit Name Description
0x0101
[7:5] Reserved Reserved.
4
Load from ROM
(read-only)
This read-only bit is set if the PINCONTROL pin was high during the last power-on.
0 = The PINCONTROL pin was low at power-on (or reset).
1 = The PINCONTROL pin was high at power-on (or reset).
3
SYSCLK XTAL enable Enables the crystal maintaining amplifier for the system clock input.
1 (default) = crystal mode (crystal maintaining amplifier enabled).
0 = external XO or other system clock source.
[2:1]
SYSCLK P divider System clock input divider.
00 (default) = 1.
01 = 2.
10 = 4.
11 = 8.
0
SYSCLK doubler enable Enable clock doubler on system clock input to reduce noise.
0 = disable.
1 (default) = enable.
Table 44. Nominal System Clock Period
1
Address Bits Bit Name Description
0x0103
[7:0] Nominal system clock period (fs) System clock period, Bits[7:0].
Default: 0x0E.
0x0104
[7:0]
System clock period, Bits[15:8].
Default: 0x67.
0x0105
[7:5] Reserved Reserved.
[4:0]
Nominal system clock period (fs)
System clock period, Bits[20:16].
Default: 0x13.
1
Note that the default setting for system clock period is 1.271566 ns, which is the period of 786.432 MHz (= 49.152 MHz × 16).
Table 45. System Clock Stability Period
Address Bits Bit Name Description
0x0106
[7:0] System clock stability period (ms)
System clock period, Bits[7:0].
Default: 0x32 (0x000032 = 50 ms).
0x0107
[7:0]
System clock period, Bits[15:8].
Default: 0x00.
0x0108 [7:5] Reserved Reserved.
4
Reset SYSCLK stability timer This autoclearing bit resets the system clock stability timer.
[3:0]
System clock stability period
System clock period, Bits[19:16].
Default: 0x00.