Datasheet

Data Sheet AD9558
Rev. B | Page 7 of 104
REFERENCE INPUTS
Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
DIFFERENTIAL OPERATION
Frequency Range
Sinusoidal Input
10 750 MHz
LVPECL Input
0.002 1250 MHz
The reference input divide-by-2 block must be
engaged for f
IN
> 705 MHz
LVDS Input
0.002
750
MHz
The reference input divide-by-2 block must be
engaged for f
IN
> 705 MHz
Minimum Input Slew Rate
40 V/μs Minimum limit imposed for jitter performance
Common-Mode Input Voltage
AC-Coupled
1.9 2 2.2 V Internally generated
DC-Coupled
1.0 2.4 V
Differential Input Voltage Sensitivity
mV
Minimum differential voltage across pins is required to
ensure switching between logic levels; instantaneous
voltage on either pin must not exceed the supply rails
f
IN
< 800 MHz 240 mV
f
IN
= 800 to 1050 MHz 320 mV
f
IN
= 1050 to 1250 MHz
400
mV
Differential Input Voltage Hysteresis 58 100 mV
Input Resistance
21 kΩ
Input Capacitance
3 pF
Minimum Pulse Width High
LVPECL
390 ps
LVDS
640 ps
Minimum Pulse Width Low
LVPECL
390 ps
LVDS
640 ps
SINGLE-ENDED OPERATION
Frequency Range (CMOS)
0.002 300 MHz
Minimum Input Slew Rate
40 V/μs Minimum limit imposed for jitter performance
Input Voltage High (V
IH
)
1.2 V to 1.5 V Threshold Setting 1.0 V
1.8 V to 2.5 V Threshold Setting
1.4 V
3.0 V to 3.3 V Threshold Setting
2.0 V
Input Voltage Low (V
IL
)
1.2 V to 1.5 V Threshold Setting
0.35 V
1.8 V to 2.5 V Threshold Setting
0.5 V
3.0 V to 3.3 V Threshold Setting
1.0 V
Input Resistance
47 kΩ
Input Capacitance
3 pF
Minimum Pulse Width High
1.5 ns
Minimum Pulse Width Low
1.5
ns