Datasheet

AD9558 Data Sheet
Rev. B | Page 68 of 104
Reg
Addr
(Hex)
Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def
DPLL Profile D (for REFD)
0x07C0 L Reference
period (up to
1.1 ms)
Nominal reference period (fs), Bits[7:0] (default: 51.44 ns =1/(19.44 MHz) for default system clock setting)
00
0x07C1 L
Nominal period (fs), Bits[15:8]
A2
0x07C2 L
Nominal period (fs), Bits[23:16]
94
0x07C3 L
Nominal period (fs), Bits[31:24]
1A
0x07C4 L
Nominal period (fs), Bits[39:32]
1D
0x07C5 L Tolerance
Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)
14
0x07C6 L
Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)
00
0x07C7 L Reserved
Inner tolerance, Bits[19:16]
00
0x07C8 L
Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm) (default: 10%)
0A
0x07C9 L
Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)
00
0x07CA L Reserved
Outer tolerance, Bits[19:16]
00
0x07CB L Validation
Validation timer (ms), Bits[7:0] (up to 65.5 seconds)
0A
0x07CC L
Validation timer (ms), Bits[15:8] (up to 65.5 seconds]
00
0x07CD L Reserved 00
0x07CE L Select base
loop filter
Reserved
Sel high PM
base loop
filter
00
0x07CF L DPLL loop BW Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz) F4
0x07D0 L Digital PLL loop bandwidth BW scaling factor[15:8] 01
0x07D1 L Reserved BW scaling
factor[16]
00
0x07D2 L DPLL
R divider
(20 bits)
R divider[7:0] 00
0x07D3 L R divider[15:8] 00
0x07D4 L Reserved Enable
REFD
divide-by-2
R divider[19:16] 00
0x07D5 DPLL
N divider
(17 bits)
Digital PLL feedback divider—Integer Part N1[7:0] 1F
0x07D6 Digital PLL feedback divider—Integer Part N1[15:8] 5B
0x07D7 Reserved Digital PLL
feedback
divider—
Integer Part
N1[16]
00
0x07D8 DPLL
fractional
feedback
divider
(24 bits)
Digital PLL fractional feedback divider—FRAC1[7:0] 00
0x07D9 Digital PLL fractional feedback divider—FRAC1[15:8] 00
0x07DA Digital PLL fractional feedback divider—FRAC1[23:16] 00
0x07DB DPLL
fractional
feedback
divider
modulus
(24 bits)
Digital PLL feedback divider modulus—MOD1[7:0] 01
0x07DC Digital PLL feedback divider modulus—MOD1[15:8] 00
0x07DD Digital PLL feedback divider modulus—MOD1[23:16] 00
0x07DE L Lock detectors Phase lock threshold (ps), Bits[7:0] BC
0x07DF L Phase lock threshold(ps), Bits[15:8] 02
0x07E0 L Phase lock fill rate[7:0] 0A
0x07E1 L Phase lock drain rate[7:0] 0A
0x07E2 L Frequency lock threshold[7:0] BC
0x07E3 L Frequency lock threshold[15:8] 02
0x07E4 L Frequency lock threshold[23:16] 00
0x07E5 L Frequency lock fill rate[7:0] 0A
0x07E6 L Frequency lock drain rate[7:0] 0A