Datasheet

Data Sheet AD9558
Rev. B | Page 63 of 104
Reg
Addr
(Hex)
Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def
0x0209
IRQ pin
output mode
Reserved
Status signal
at IRQ pin[1:0]
Use IRQ pin
for status
signal
IRQ pin driver type[1:0]
1F
0x020A IRQ mask Reserved SYSCLK
unlocked
SYSCLK
locked
APLL
unlocked
APLL
locked
APLL cal
complete
APLL cal
started
00
0x020B Reserved Pin
program
end
Sync
distribution
Watchdog
timer
EEPROM fault EEPROM
complete
00
0x020C Switching Closed Freerun Holdover Frequency
unlocked
Frequency
locked
Phase unlocked Phase locked 00
0x020D Reserved History
updated
Frequency
unclamped
Frequency
clamped
Phase slew
unlimited
Phase slew
limited
00
0x020E Reserved REFB
validated
REFB
fault
cleared
REFB
fault
Reserved REFA
validated
REFA fault
cleared
REFA fault 00
0x020F Reserved REFD
validated
REFD
fault
cleared
REFD fault Reserved REFC
validated
REFC fault
cleared
REFC fault 00
0x0210 Watchdog
Timer 1
Watchdog timer (ms), Bits[7:0] 00
0x0211 Watchdog timer (ms), Bits[15:8] 00
0x0300 Freerun
frequency TW
30-bit free run frequency tuning word[7:0] 11
0x0301 30-bit free run frequency tuning word[15:8] 15
0x0302 30-bit free run frequency tuning word[23:16] 64
0x0303 Reserved 30-bit free run frequency tuning word[29:24] 1B
0x0304 Digital
oscillator
control
Reserved DCO
4-level
output
Reserved
(must be 1b)
Reserved Reset SDM 10
0x0305 Reserved 00
0x0306 DPLL
frequency
clamp
Lower limit of pull-in range[7:0] 51
0x0307 Lower limit of pull-in range[15:8] B8
0x0308 Reserved Lower limit of pull-in range[19:16] 02
0x0309 Upper limit of pull-in range[7:0] 3E
0x030A
Upper limit of pull-in range[15:8]
0A
0x030B Reserved Upper limit of pull-in range[19:16] 0B
0x030C Closed-loop
phase lock
offset
[±0.5 ms]
Fixed phase lock offset (signed; ps), Bits[7:0] 00
0x030D Fixed phase lock offset (signed; ps), Bits[15:8] 00
0x030E Fixed phase lock offset (signed; ps), Bits[23:16] 00
0x030F Reserved Fixed phase lock offset (signed; ps), Bits[29:24] 00
0x0310 Incremental phase lock offset step size (ps/step), Bits[7:0] (up to 65.5 ns/step) 00
0x0311 Incremental phase lock offset step size (ps/step), Bits[15:8] (up to 65.5 ns/step) 00
0x0312 Phase slew
rate limit
Phase slew rate limit (µs/sec), Bits[7:0] (315 µs/sec up to 65.536 ms/sec) 00
0x0313 Phase slew rate limit (µs/sec), Bits[15:8] (315 µs/sec up to 65.536 ms/sec) 00
0x0314 Holdover
history
History accumulation timer (ms), Bits[7:0] (up to 65 seconds) 0A
0x0315 History accumulation timer (ms), Bits[15:8] (up to 65 seconds) 00
0x0316 History mode Reserved Single
sample
fallback
Persistent
history
Incremental average 00
0x0317 L Base Loop
Filter A
coefficient set
(high phase
margin)
HPM Alpha-0[7:0] 8C
0x0318 L HPM Alpha-0[15:8] AD
0x0319 L Reserved HPM Alpha-1[6:0] 4C
0x031A L HPM Beta-0[7:0] F5
0x031B L HPM Beta-0[15:8] CB
0x031C L Reserved HPM Beta-1[6:0] 73
0x031D L HPM Gamma-0[7:0] 24
0x031E L HPM Gamma-0[15:8] D8
0x031F L Reserved HPM Gamma-1[6:0] 59
0x0320 L HPM Delta-0[7:0] D2
0x0321 L HPM Delta-0[15:8] 8D
0x0322 L Reserved HPM Delta-1[6:0] 5A