Datasheet
AD9558 Data Sheet
Rev. B | Page 60 of 104
Table 33. Preset Output Frequencies for Hard Pin and Soft Pin Programming
Freq ID Frequency (MHz) Frequency Description
Hard Pin Program
PINCONTROL = High
Soft Pin Program
PINCONTROL = Low,
Register 0x0C01[3:0]
M3
M2
M1
B7
B6
B5
B4
0 19.44 19.44 MHz 0 0 0 0 0 0 0
1
25
25 MHz
0
0
½
0
0
0
1
2 125 125 MHz 0 0 1 0 0 1 0
3
156.7071 156.25 MHz × 1027/1024 0 ½ 0 0 0 1 1
4
622.08 622.08 MHz 0 ½ ½ 0 1 0 0
5
625 625 MHz 0 ½ 1 0 1 0 1
6
644.53125 625 MHz × 33/32 0 1 0 0 1 1 0
7
657.421875 657.421875 MHz 0 1 ½ 1 1 1
8
660.184152 657.421875 MHz × 239/238 0 1 1 1 0 0 0
9
666.5143 622.08 MHz × 255/238 ½ 0 0 1 0 0 1
10
669.3266 622.08 MHz × 255/237 ½ 0 ½ 1 0 1 0
11
672.1627 622.08 MHz × 255/236 ½ 0 1 1 0 1 1
12
690.5692
644.53125 MHz × 255/238
½
½
0
1
1
0
0
13 693.4830 644.53125 MHz × 255/237 ½ ½ ½ 1 1 0 1
14
698.8124 622.08 MHz × 255/237 ½ ½ 1 1 1 1 0
15
704.380580 657.421875 MHz × 255/238 ½ 1 0 1 1 1 1
Table 34. System Clock Configuration in Hard Pin and Soft Pin Programming Modes
Freq ID Frequency (MHz) System Clock Configuration
Hard Pin Program
PINCONTROL = High,
IRQ Pin
Soft Pin Program
PINCONTROL = Low,
Register 0x0C02[1:0]
Equivalent
System Clock
PLL Register
Settings
IRQ Pin Bit 1 Bit 0
0 49.152 XTAL mode, doubler on, N = 8 0 0 0 0001, 0000, 1000
1
49.152 XTAL mode off, doubler on, N = 8 ½ 0 1
2
24.576 XTAL mode, doubler on, N = 16 1 1 0
3
98.304
XTAL mode off, doubler off, N = 8
N/A
1
1
HARD PIN PROGRAMMING MODE
The state of the PINCONTROL pin at power-up controls whether
or not the chip is in hard pin programming mode. Setting the
PINCONTROL pin high disables the I
2
C protocol, although the
register map can be accessed via the SPI protocol.
The M0, M5, and M4 pins select one of 16 input frequencies, and
the M3 to M1 pins select one of 16 possible output frequencies. See
Table 32 and Table 33 for details.
The system clock configuration is controlled by the state of the
IRQ pin at startup (see Table 34 for details). The digital PLL
loop bandwidth, reference input frequency accuracy tolerance
ranges, and DPLL phase margin selection are not available in
hard pin programming mode unless the user uses the serial port
to change their default values.
When in hard pin programming mode, the user must set
Register 0x0200[0] = 1 to activate the IRQ, REF status, and PLL
lock status signals at the multifunction pins.