Datasheet

Data Sheet AD9558
Rev. B | Page 19 of 104
Pin No. Mnemonic
Input/
Output Pin Type Description
43
REFA I
Differential
input
Reference A Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.
44
AAREFAEE
I
Differential
input
Complementary Reference A Input. This pin is the complementary input to Pin 43.
45, 46,
51, 52
DVDD3 I Power 3.3 V Digital (Reference Input) Power Supply.
47 REFC I
Differential
input
Reference C Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.
48
AAREFCEE
I
Differential
input
Complementary Reference C Input. This pin is the complementary input to Pin 47.
49
REFD I
Differential
input
Reference D Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.
50
AAREFDEE
I
Differential
input
Complementary Reference D Input. This pin is the complementary input to Pin 49.
53
REFB I
Differential
input
Reference B Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.
54
AAREFBEE
I
Differential
input
Complementary Reference B Input. This pin is the complementary input to Pin 53.
57, 58,
59, 60,
61, 62,
63
M0, M1, M2,
M3, M4, M5,
M6
I/O 3.3 V CMOS
Configurable I/O Pins. These pins are configured under program control. The M7 pin
(Pin 41) is the last pin of this group.
64 DVDD3 I Power 3.3 V Digital Supply.
EP
VSS O Exposed pad The exposed pad must be connected to ground (VSS).