Datasheet

Data Sheet AD9558
Rev. B | Page 13 of 104
SERIAL PORT SPECIFICATIONS—I
2
C MODE
Table 16.
Parameter Min Typ Max Unit Test Conditions/Comments
SDA, SCL (AS INPUT)
Input Logic 1 Voltage
0.7 ×
DVDD3
V
Input Logic 0 Voltage
0.3 ×
DVDD3
V
Input Current
−10 +10 µA For V
IN
= 10% to 90% DVDD3
Hysteresis of Schmitt Trigger Inputs
0.015 ×
DVDD3
Pulse Width of Spikes That Must Be Suppressed by
the Input Filter, t
SP
50 ns
SDA (AS OUTPUT)
Output Logic 0 Voltage
0.4 V I
O
= 3 mA
Output Fall Time from V
IHmin
to V
ILmax
20 + 0.1 C
b
2F
1
250 ns 10 pF ≤ C
b
≤ 400 pF
TIMING
SCL Clock Rate
400 kHz
Bus-Free Time Between a Stop and Start
Condition, t
BUF
1.3 µs
Repeated Start Condition Setup Time, t
SU; STA
0.6
µs
Repeated Hold Time Start Condition, t
HD; STA
0.6 µs
After this period, the first clock pulse is
generated
Stop Condition Setup Time, t
SU; STO
0.6 µs
Low Period of the SCL Clock, t
LOW
1.3 µs
High Period of the SCL Clock, t
HIGH
0.6 µs
SCL/SDA Rise Time, t
R
20 + 0.1 C
b
1
300 ns
SCL/SDA Fall Time, t
F
20 + 0.1 C
b
1
300 ns
Data Setup Time, t
SU; DAT
100 ns
Data Hold Time, t
HD; DAT
100 ns
Capacitive Load for Each Bus Line, C
b
1
400 pF
1
C
b
is the capacitance (pF) of a single bus line.
JITTER GENERATION
Jitter generation (random jitter) uses 49.152 MHz crystal for system clock input.
Table 17.
Parameter Min Typ Max Unit Test Conditions/Comments
JITTER GENERATION
System clock doubler enabled;
high phase margin mode enabled;
Register 0x0405 = 0x20; Register 0x0403 =
0x07; Register 0x0400 = 0x81;
in cases where multiple driver types are
listed, both driver types were tested at
those conditions, and the one with higher
jitter is quoted, although there is usually
not a significant jitter difference between
the driver types
f
REF
= 19.44 MHz; f
OUT
= 622.08 MHz; f
LOOP
= 50 Hz
HSTL Driver
Bandwidth: 5 kHz to 20 MHz 304 fs rms
Bandwidth: 12 kHz to 20 MHz
296
fs rms
Bandwidth: 20 kHz to 80 MHz 300 fs rms
Bandwidth: 50 kHz to 80 MHz
266 fs rms
Bandwidth: 16 MHz to 320 MHz
185 fs rms