Datasheet

Data Sheet AD9558
Rev. B | Page 11 of 104
DIGITAL PLL
Table 12.
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL PLL
Phase-Frequency Detector (PFD)
Input Frequency Range
2 100 kHz
Loop Bandwidth
0.1 2000 Hz Programmable design parameter
Phase Margin
30 89 Degrees Programmable design parameter
Closed-Loop Peaking
<0.1 dB
Programmable design parameter ;
part can be programmed for <0.1 dB peaking in
accordance with Telcordia GR-253 jitter transfer
Reference Input (R) Division Factor
1 2
20
1, 2, …, 1,048,576
Integer Feedback (N1) Division Factor
180 2
17
180, 181, …, 131,072
Fractional Feedback Divide Ratio
0 0.999 Maximum value: 16,777,215/16,777,216
DIGITAL PLL LOCK DETECTION
Table 13.
Parameter Min Typ Max Unit Test Conditions/Comments
PHASE LOCK DETECTOR
Threshold Programming Range
0.001 65.5 ns
Threshold Resolution
1 ps
FREQUENCY LOCK DETECTOR
Threshold Programming Range
0.001 16,700 ns Reference-to-feedback period difference
Threshold Resolution
1 ps
HOLDOVER SPECIFICATIONS
Table 14.
Parameter Min Typ Max Unit Test Conditions/Comments
HOLDOVER SPECIFICATIONS
Initial Frequency Accuracy
<0.01 ppm
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference prior
to entering holdover; compliant with GR-1244
Stratum 3