Datasheet

Data Sheet AD9558
Rev. B | Page 103 of 104
Table 130. Multifunction Pin Input Functions (D7 = 0)
Register Value Input Function Equivalent Control Register
0x00 Reserved, high-Z input
0x01
I/O update Register 0x0005, Bit 0
0x02
Full power-down Register 0x0A00, Bit 0
0x03
Clear watchdog Register 0x0A03, Bit 0
0x04
Clear all IRQs
Register 0x0A03, Bit 1
0x05 Tuning word history reset Register 0x0A03, Bit 2
0x06 to 0x0E
Reserved
0x10
User holdover Register 0x0A01, Bit 6
0x11
User free run Register 0x0A01, Bit 5
0x12
Reset incremental phase offset
Register 0x0A0A, Bit 2
0x13 Increment incremental phase offset Register 0x0A0A, Bit 0
0x14
Decrement incremental phase offset Register 0x0A0A, Bit 1
0x15 to 0x1F
Reserved
0x20
Override Reference Monitor A Register 0x0A0C, Bit 0
0x21
Override Reference Monitor B Register 0x0A0C, Bit 1
0x22
Override Reference Monitor C
Register 0x0A0C, Bit 2
0x23 Override Reference Monitor D Register 0x0A0C, Bit 3
0x24 to 0x2F
Reserved
0x30
Force Validation Timeout A Register 0x0A0B, Bit 0
0x31
Force Validation Timeout B Register 0x0A0B, Bit 1
0x32
Force Validation Timeout C Register 0x0A0B, Bit 2
0x33
Force Validation Timeout D Register 0x0A0B, Bit 3
0x34 to 0x3F
Reserved
0x40
Enable OUT0 Register 0x0501, Bit 0
0x41
Enable OUT1 Register 0x0505, Bit 0
0x42
Enable OUT2 Register 0x0506, Bit 0
0x43
Enable OUT3
Register 0x050A, Bit 0
0x44 Enable OUT4 Register 0x050B, Bit 0
0x45
Enable OUT5 Register 0x050F, Bit 0
0x46
Enable OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 Register 0x0501/0x0505/0x0506/0x050A/0x050B/0x050F, Bit 0
0x47
Soft sync clock distribution outputs Register 0x0A02, Bit 1
0x48 to 0x7F
Reserved