Datasheet

Data Sheet AD9557
Rev. B | Page 83 of 92
Address Bits Bit Name Description
0x0C06
[7:5] Reserved Reserved
4
Sel high PM base
loop filter
0 = base loop filter with normal (70°) phase margin (default).
1 = base loop filter with high (88.5°) phase margin.
(<0.1 dB peaking in closed-loop transfer function).
[3:2] DPLL loop BW Scales the DPLL loop BW while in soft pin mode.
00 (default) = 50 Hz.
01 = 1 Hz.
10 = 10 Hz.
11 = 100 Hz.
[1:0] Reference input
frequency tolerance
Scales the input frequency tolerance while in soft pin mode.
00 (default) = outer tolerance: 10%; inner tolerance: 8% (for general conditions).
01 = outer tolerance: 12 ppm; inner tolerance: 9.6 ppm (for Stratum 3).
10 = outer tolerance: 48 ppm; inner tolerance: 38 ppm (for SMC clock standard).
11 = outer tolerance: 200 ppm; inner tolerance: 160 ppm (for XTAL system clock).
0x0C07
[7:1] Reserved Reserved.
0 Soft pin start transfer Autoclearing register. 1 = initiates ROM download without resetting the part/register map.
After ROM download is complete, this register is reset.
0x0C08
[7:1] Reserved Reserved.
0
Soft pin reset
Autoclearing register; resets the part like soft reset (Register 0x0000[5]), except that this reset
function initiates a soft pin ROM download without resetting the part/register map. After ROM
download is complete, this register is pulled back to zero.
STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D14)
All bits in Register 0x0D00 to Register 0x0D14 are read only. To show the latest status, these registers require an I/O update (Register 0x0005 =
0x01) immediately before being read.
Table 98. EEPROM Status
Address Bits Bit Name Description
0x0D00 [7:4] Reserved Reserved.
3
Pin program ROM
load process
The control logic sets this bit when data is being read from the ROM.
2 Fault detected An error occurred while saving data to or loading data from the EEPROM.
1
Load in progress The control logic sets this bit while data is being read from the EEPROM.
0
Save in progress The control logic sets this bit while data is being written to the EEPROM.
Table 99. SYSCLK Status
Address Bits Bit Name Description
0x0D01
7 Reserved Reserved.
6
DPLL_APLL_Lock Indicates the status of the DPLL and APLL.
0 = either the DPLL or the APLL is unlocked.
1 = both the DPLL and APLL are locked.
5
All PLLs locked Indicates the status of the system clock PLL, APLL, and DPLL.
0 = system clock PLL or APLL or DPLL is unlocked.
1 = all three PLLs (system clock PLL, APLL, and DPLL) are locked.
4 APLL VCO status 1 = OK.
0 = off/clocks are missing.
3
APLL cal in process
The control logic holds this bit set while the amplitude calibration of the APLL VCO is in progress.
2 APLL lock Indicates the status of the APLL.
0 = unlocked.
1 = locked.
1
System clock stable The control logic sets this bit when the device considers the system clock to be stable (see the
System Clock Stability Timer section).
0 = not stable (the system clock stability timer has not expired yet).
1 = stable (the system clock stability timer has expired).
0 SYSCLK lock detect Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked.