Datasheet

AD9557 Data Sheet
Rev. B | Page 80 of 92
Reset Functions (Register 0x0A03)
Table 89. Reset Functions
Address
Bits
Bit Name
Description
0x0A03
(autoclear)
7 Reserved Default: 0b.
6 Clear LF Setting this bit clears the digital loop filter (intended as a debug tool).
5
Clear CCI Setting this bit clears the CCI filter (intended as a debug tool).
4
Reserved Default: 0b.
3 Clear auto sync Setting this bit resets the automatic synchronization logic (see Register 0x0500).
2
Clear TW history Setting this bit resets the tuning word history logic (part of holdover functionality).
1
Clear all IRQs Setting this bit clears the entire IRQ monitor register (Register 0x0D02 to Register 0x0D07). It
is the equivalent of setting all the bits of the IRQ clearing register (Register 0x0A04 to
0x0A0D).
0
Clear watchdog timer Setting this bit resets the watchdog timer (see Register 0x0210 and Register 0x0211). If the
timer times out, it simply starts a new timing cycle. If the timer has not yet timed out, it restarts
at time zero without causing a timeout event. Continuously resetting the watchdog timer at
intervals of less than its timeout period prevents the watchdog timer from generating a
timeout event.
IRQ Clearing (Register 0x0A04 to Register 0x0A09)
The IRQ clearing registers are identical in format to the IRQ monitor registers (Register 0x0D02 to Register 0x0D09). When set to Logic 1,
an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ clearing
register is an autoclearing register.
Table 90. IRQ Clearing for SYSCLK
Address Bits Bit Name Description
0x0A04
[7:6] Reserved Reserved
5
SYSCLK unlocked Clears SYSCLK unlocked IRQ
4 SYSCLK locked Clears SYSCLK locked IRQ
3
APLL unlocked Clears Output PLL unlocked IRQ
2
APLL locked Clears Output PLL locked IRQ
1
APLL Cal ended Clears APLL calibration complete IRQ
0
APLL Cal started Clears APLL calibration started IRQ
Table 91. IRQ Clearing for Distribution Sync, Watchdog Timer and EEPROM
Address Bits Bit Name Description
0x0A05
[7:5] Reserved Reserved
4 Pin program end Clears pin program end IRQ
3
Sync clock distribution Clears distribution sync IRQ
2 Watchdog timer Clears watchdog timer IRQ
1
EEPROM fault Clears EEPROM fault IRQ
0
EEPROM complete Clears EEPROM complete IRQ
Table 92. IRQ Clearing for the Digital PLL
Address Bits Bit Name Description
0x0A06
7 Switching Clears switching IRQ
6
Closed Clears closed IRQ
5
Freerun Clears free run IRQ
4 Holdover Clears holdover IRQ
3
Frequency unlocked
Clears frequency unlocked IRQ
2 Frequency locked Clears frequency locked IRQ
1 Phase unlocked Clears phase unlocked IRQ
0
Phase locked
Clears phase locked IRQ