Datasheet

Data Sheet AD9557
Rev. B | Page 79 of 92
REFB Profile (Register 0x0740 to Register 0x0766)
The REFB profile registers, Register 0x0740 to Register 0x0766, are identical to the REFA profile registers, Register 0x0700 to Register 0x0726.
OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A0D)
Table 86. General Power-Down
Address Bits Bit Name Description
0x0A00
7 Soft reset exclude regmap Resets device but retain programmed register values (default is not reset)
6
DCO power-down Places DCO in deep sleep mode (default is not powered down)
5 SYSCLK power-down Places SYSCLK input and PLL in deep sleep mode (default is not powered down)
4
Reference input power-down Places reference clock inputs in deep sleep mode (default is not powered down)
3
TDC power-down Places the time-to-digital converter in deep sleep mode (default is not powered down)
2 APLL power-down Places the Output PLL in deep sleep mode (default is not powered down)
1
Clock dist power-down Places the clock distribution outputs in deep sleep mode (default is not powered down)
0
Full power-down Places the entire device in deep sleep mode (default is not powered down)
Table 87. Loop Mode
Address Bits Bit Name Description
0x0A01
7 Reserved Reserved.
6
User holdover Forces the device into holdover mode (default is not forced holdover mode).
If a tuning word history is available, then the history tuning word specifies the DCO
output frequency. Otherwise, the free run frequency tuning word register specifies the
DCO output frequency.
The phase and frequency lock detectors are forced into the unlocked state.
5 User freerun Forces the device into user free run mode (default is not forced user free run mode).
The free run frequency tuning word register specifies the DCO output frequency. When
the user freerun bit is set, it overrides the user holdover bit (Address 0x0A01, Bit 6).
[4:2]
REF switchover mode Selects the operating mode of the reference switching state machine.
Reference Switchover Mode, Bits[2:0];
Register 0x0A01[4:2] Reference Selection Mode
000 (default) Automatic revertive mode
001
Automatic non-revertive mode
010 Manual reference select
(with automatic fallback mode)
011 Manual reference select mode
(with auto-holdover)
100 Full manual mode (no auto-holdover)
101 Not used
110 Not used
111 Not used
1
Reserved Reserved.
0 User reference in manual
switchover mode
Input reference when reference switchover mode (Register 0x0A01, Bits[4:2]) = 100.
0 (default) = Input Reference A.
1 = Input Reference B.
Table 88. Cal/Sync
Address Bits Bit Name Description
0x0A02
[7:2] Reserved Default: 0x00
1
Soft sync clock distribution
Setting this bit initiates synchronization of the clock distribution output (default: 0b).
Nonmasked outputs stall when value is 1b, restart is initialized on 1b to 0b transition.
0 Reserved Default: 0b.