Datasheet

Data Sheet AD9557
Rev. B | Page 65 of 92
REGISTER MAP BIT DESCRIPTIONS
SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)
Table 36. Serial Configuration (Note that the contents of Register 0x0000 are not stored to the EEPROM.)
Address Bits Bit Name Description
0x0000
7 SDO enable Enables SPI port SDO pin.
1 = 4-wire (SDO pin enabled).
0 (default) = 3-wire.
6 LSB first/increment address Bit order for SPI port.
1 = least significant bit and byte first.
Register addresses are automatically incremented in multibyte transfers.
0 (default) = most significant bit and byte first.
Register addresses are automatically deccremented in multibyte transfers.
5 Soft reset Device reset (invokes an EEPROM download or pin program ROM download if EEPROM
or pin program is enabled. See the EEPROM and Pin Configuration and Function
Descriptions for details.
[4:0] Reserved Reserved.
Table 37. Readback Control
Address Bits Bit Name Description
0x0004
[7:1] Reserved Reserved.
0 Read buffer register For buffered registers, serial port read-back reads from actual (active) registers instead of
the buffer.
1 = reads buffered values that take effect on next assertion of I/O update.
0 (default) = reads values currently applied to the device’s internal logic.
Table 38. Soft I/O Update
Address Bits Bit Name Description
0x0005
[7:1] Reserved Reserved.
0
I/O update Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the device’s
internal control registers. Unless a register is marked as live (as indicated by an L in the
Opt column of the register map), the user must write to this bit before any register
settings can take effect and before a read-only register can be updated with the most
current value.
This is an autoclearing bit.
Table 39. User Scratch Pad
Address Bits Bit Name Description
0x0006
[7:0] User scratch pad[7:0] User programmable EEPROM ID registers. These registers enable users to write a unique
code of their choosing to keep track of revisions to the EEPROM register loading. It has
no effect on part operation.
0 = default.
0x0007 [7:0] User scratch pad[15:8]
SILICON REVISION (REGISTER 0x000A)
Table 40. Silicon Revision
Address Bits Bit Name Description
0x000A
[7:0]
Silicon revision
This read-only register identifies the revision level of the AD9557.
CLOCK PART SERIAL ID (REGISTER 0x000C TO REGISTER 0x000D)
Table 41. Clock Part Family ID
Address Bits Bit Name Description
0x000C
[7:0] Clock part family ID[7:0] This read-only register (along with Register 0x000D) uniquely identifies an AD9557 or
AD9558. No other part in the ADI AD95xx family has a value of 0x0001 in these two registers.
Default: 0x01 for the AD9557 and AD9558.
0x000D
[7:0] Clock part family ID[15:8] This register is a continuation of Register 0x000C.
Default: 0x00 for the AD9557 and AD9558.