Datasheet

Data Sheet AD9557
Rev. B | Page 59 of 92
Reg
Addr
(Hex)
Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def
Reference Inputs
0x0600
Reference
power-
down
Reserved Reserved
REFB
power-
down
REFA
power-
down
00
0x0601
Reference
logic type
Reserved REFB logic type[1:0] REFA logic type[1:0] 00
0x0602
Reference
priority
Reserved REFB priority[1:0] REFA priority[1:0] 00
0x0603 Reserved Reserved 00
Profile A (for REFA)
0x0700 L
Reference
period
(up to
1.1 ms)
Nominal reference period (fs), Bits[7:0] (default: 51.44 ns =1/(19.44 MHz) for default system clock setting) C9
0x0701 L Nominal period (fs), Bits[15:8] EA
0x0702 L Nominal period (fs), Bits[23:16] 10
0x0703 L Nominal period (fs), Bits[31:24] 03
0x0704 L Nominal period (fs), Bits[39:32] 00
0x0705 L
Frequency
tolerance
Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%) 14
0x0706 L Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm) 00
0x0707 L Reserved Inner tolerance, Bits[19:16] 00
0x0708 L Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm) (default: 10%) 0A
0x0709 L Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm) 00
0x070A L Reserved Outer tolerance, Bits[19:16] 00
0x070B L Validation Validation timer (ms), Bits[7:0] (up to 65.5 seconds) 0A
0x070C L Validation timer (ms), Bits[15:8] (up to 65.5 seconds] 00
0x070D L Reserved Reserved 00
0x070E L
Select base
loop filter
Reserved
Sel high PM
base loop
filter
00
0x070F L
DPLL loop
BW
Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz) F4
0x0710 L Digital PLL loop BW scaling factor[15:8] 01
0x0711 L Reserved
BW scaling
factor[16]
00
0x0712 L
DPLL
R divider
(20 bits)
R divider[7:0] C5
0x0713 L R divider[15:8] 00
0x0714 L Reserved
Enable REFA
divide-by-2
R divider[19:16] 00
0x0715
DPLL
N divider
(17 bits)
Digital PLL feedback divider—Integer Part N1[7:0] 6B
0x0716 Digital PLL feedback divider—Integer Part N1[15:8] 07
0x0717 Reserved
Digital PLL
feedback
divider—
Integer Part
N1[16]
00
0x0718
DPLL
fractional
feedback
divider
(24 bits)
Digital PLL fractional feedback divider—FRAC1[7:0] 04
0x0719 Digital PLL fractional feedback divider—FRAC1[15:8] 00
0x071A Digital PLL fractional feedback divider—FRAC1[23:16] 00
0x071B
DPLL
fractional
feedback
divider
modulus
(24 bits)
Digital PLL feedback divider modulus—MOD1[7:0] 05
0x071C Digital PLL feedback divider modulus—MOD1[15:8] 00
0x071D Digital PLL feedback divider modulus—MOD1[23:16] 00
0x071E L
Lock
detectors
Phase lock threshold[7:0] (ps) BC
0x071F L Phase lock threshold[15:8] (ps) 02
0x0720 L Phase lock fill rate[7:0] 0A
0x0721 L Phase lock drain rate[7:0] 0A
0x0722 L Frequency lock threshold[7:0] BC
0x0723 L Frequency lock threshold[15:8] 02
0x0724 L Frequency lock threshold[23:16] 00
0x0725 L Frequency lock fill rate[7:0] 0A
0x0726 L Frequency lock drain rate[7:0] 0A