Datasheet
Data Sheet AD9557
Rev. B | Page 17 of 92
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NOTES
1. THE EXPOSED
PAD MUST BE CONNECTED TO GROUND (VSS).
1
IRQ
2
SCLK/SC
L
3
SDIO/SDA
4SDO
5CS
6
DVDD
7A
VDD
8XO
A
9XOB
10AVDD
23 AVDD
24
AVDD
25 RESET
26 PINCONTROL
27
SYNC
28 RE
FA
29 REFA
30 DVDD3
22 AVDD
21 LF_VCO2
1
1
A
VDD
12
OUT1
13
OUT1
15
OUT0
17
A
VDD
16
OUT0
18
A
VDD
19
A
VDD3
20
LDO_VCO2
14
A
VDD3
33
REFB
34
DVDD
35
DVDD
36
M0
37
M1
38
M2
39
M3
40
DVDD3
32
REFB
31
DVDD3
TOP VIEW
(Not to Scale)
AD9557
09197-002
Figure 2. Pin Configuration
Table 20. Pin Function Descriptions
Pin No. Mnemonic
Input/
Output Pin Type Description
1
IRQ O 3.3 V CMOS Interrupt Request Line.
2
SCLK/SCL I 3.3 V CMOS Serial Programming Clock (SCLK) in SPI Mode. Data clock for serial programming.
Serial Clock Pin (SCL) in I
2
C Mode.
3 SDIO/SDA I/O 3.3 V CMOS Serial Data Input/Output (SDIO) in SPI Mode. When the device is in 4-wire SPI
mode, data is written via this pin. In 3-wire mode, both data reads and writes
occur on this pin. There is no internal pull-up/pull-down resistor on this pin.
Serial Data Pin (SDA) in I
2
C Mode.
4 SDO O 3.3 V CMOS Serial Data Output. Use this pin to read data in 4-wire mode. There is no internal
pull-up/pull-down resistor on this pin. This pin is high impedance in the default
3-wire mode.
5
A
CS
E
I 3.3 V CMOS Chip Select (SPI), Active Low. When programming a device, this pin must be held
low. In systems where more than one AD9557 is present, this pin enables
individual programming of each AD9557. This pin has an internal 10 kΩ pull-up
resistor.
6, 34, 35
DVDD I Power 1.8 V Digital Supply.
7, 10, 22,
23, 24
AVDD I Power 1.8 V Analog Power Supply.
8
XOA I Differential
input
System Clock Input. XOA contains internal dc biasing and should be ac-coupled
with a 0.01 μF capacitor, except when using a crystal, in which case connect the
crystal across XOA and XOB. Single-ended 1.8 V CMOS is also an option but can
introduce a spur if the duty cycle is not 50%. When using XOA as a single-ended
input, connect a 0.01 μF capacitor from XOB to ground.
9
XOB I Differential
input
Complementary System Clock Input. Complementary signal to XOA. XOB contains
internal dc biasing and should be ac-coupled with a 0.01 μF capacitor, except
when using a crystal, in which case connect the crystal across XOA and XOB.
11, 17, 18
AVDD I Power 1.8 V Analog (Output Divider and Drivers) Power Supply.
12 A
OUT1
E
O HSTL, LVDS, or
1.8 V CMOS
Complementary Output 1. This output can be configured as HSTL, LVDS, or
single-ended 1.8 V CMOS.
13 OUT1 O HSTL, LVDS, or
1.8 V CMOS
Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations
section.
14, 19
AVDD3 I Power 3.3 V Analog Power Supply.