Datasheet

AD9553
Rev. A | Page 37 of 44
PLL and Output Frequency Control (Register 0x11 to Register 0x19)
Table 31.
Address Bit Bit Name Description
0x11 [7:0] Unused Unused.
0x12 [7:0] Feedback divider (N) Bits[19:12] of the 20-bit feedback divider (N).
0x13 [7:0] Feedback divider (N) Bits[11:4] of the 20-bit feedback divider (N).
0x14 [7:4] Feedback divider (N)
Bits[3:0] of the 20-bit feedback divider (N). Default is N = 0x80000 (524,288). The feedback
divider bits are ineffective unless Register 0x14[3] = 1.
3
Enable SPI control of
feedback divider
Enables SPI port control of the feedback divider value (N).
0 = the A3 to A0 and Y5 to Y0 pins define N per Table 16 (default).
1 = the 20-bit value in the feedback divider register defines N.
2
Enable SPI control of
output dividers
Enables SPI port control of the output dividers P
0
, P
1
, and P
2
.
0 = the Y5 to Y0 pins define the output divider values per Table 15 (default).
1 = the SPI port registers (0x15, 0x16, 0x18) define the output divider values.
1 Unused Unused.
0 Reset PLL Controls initialization of the PLL.
0 = normal operation (default).
1 = resets the counters and logic associated with the PLL but does not affect the output dividers.
0x15 [7:0] P
1
divider Bits[9:2] of the 11-bit P
1
divider.
0x16 [7:6] P
1
divider
Bits[1:0] of the 11-bit P
1
divider (the default P
1
divider register value is 128 decimal). The P
1
divider bits are ineffective unless Register 0x14[2] = 1.
[5:0] P
2
divider Bits[9:4] of the 11-bit P
2
divider.
0x17 [7:4] P
2
divider Bits[3:0] of the 11-bit P
2
divider. The P
2
divider bits are ineffective unless Register 0x14[2] = 1.
3 Enable test port Enables use of the LOCKED pin as a test port.
0 = the LOCKED pin indicates PLL status (default).
1 = the LOCKED pin outputs a test signal per Register 0x17[2:1].
[2:1] Test mux Test mux select bits.
00 = crystal oscillator output (XO).
01 = PFD pump up clock divided-by-2 (UP/2).
10 = PFD reference input clock divided-by-2 (FPFD/2).
11 = PFD feedback clock divided-by-2 (FDBK/2).
0 Unused Unused.
0x18 [7:5] P
0
divider Bits[2:0] of the P
0
divider. The P
0
divider bits are ineffective unless Register 0x14[2] = 1.
000 = invalid.
001 = divide-by-5.
010 = divide-by-6.
011 = divide-by-7.
100 = divide-by-8.
101 = divide-by-9.
110 = divide-by-10.
111 = divide-by-11.
[4:0] Unused Unused.
0x19 [7:0] Unused Unused.