Datasheet

AD9553
Rev. A | Page 25 of 44
PIN
DECODE
LOGIC
OM[2:0]
0
1
3
3
DRIVER
OUT1
OUTPUT
CONTROL
OUTPUT
CONTROL
2
3
3
3
DRIVE
STRENGTH
REGISTER 0x32
REGISTER 0x34
MODE
CONTROL
ENABLE
SPI
CONTROL
POWER-
DOWN
CMOS
POLARITY
DRIVE
STRENGTH
MODE
CONTROL
POWER-
DOWN
CMOS
POLARITY
2
DRIVER
OUT2
2
0
1
2
3
3
MODE
CONTROL
0
REGISTER
DEFAULT VALUES
SHOWN IN RED
101 0001
0101 0001
3
ENABLE
SPI
CONTROL
BITS
[5:3]
BITS
[2:1]
BIT 0 BIT 7 BIT 6
BITS
[5:3]
BITS
[2:1]
BIT 0 BIT 7 BIT 6
08565-104
Figure 31. Output Driver Control
Output Driver Polarity (CMOS)
When the mode control bits indicate the CMOS logic family
(see Table 19), the user has control of the logic polarity asso-
ciated with each CMOS output pin. Driver polarity defines how
the logic level (Logic 1 or Logic 0) at a CMOS output pin relates
to the logic state (logic true or logic false). Normal polarity
equates Logic 1/Logic 0 to logic true/logic false, while inverted
polarity equates Logic 0/Logic 1 to logic true/logic false. Bit[2]
of the OUT1 and OUT2 driver control registers establishes the
CMOS polarity of the associated output driver (see Figure 31).
Output Drive Strength (CMOS or LVDS)
When the mode bits indicate the CMOS or LVDS logic family
(see Table 19), the user can select whether the output driver
uses weak or strong drive capability. Bit 7 of the OUT1 and
OUT2 driver control registers control the drive strength of
the associated output driver (see Figure 31). In the case of the
CMOS family, the strong setting allows for driving increased
capacitive loads. In the case of the LVDS family, the nominal
weak and strong drive currents are 3.5 mA and 7 mA, respectively.
Output Power Down
The AD9553 supports the option of independent power-down
of the output drivers. Bit 6 of the OUT1 and OUT2 driver control
registers controls the power-down function (see Figure 31). When
Bit 6 is Logic 0, the associated output driver is active. When Bit 6 is
Logic 1, the associated output driver is in power-down mode.