Datasheet

AD9553
Rev. A | Page 24 of 44
The mode control bits establish the logic family and output pin
function of the associated output driver per Table 19
. The logic
families include LVDS, LVPECL, and CMOS. Because both
output drivers support the LVDS and LVPECL logic families,
each driver has two pins to handle the differential signals associated
with these two logic families. The OUT1 driver uses the OUT1
and
OUT1
pins and the OUT2 driver uses the OUT2 and
OUT2
pins. However, the CMOS logic family handles only single-ended
signals, thereby requiring only one pin. Even though CMOS
only requires one pin, both pins of OUT1 and both pins of
OUT2 have a dedicated CMOS driver.
Note that the LVPECL mode of the AD9553 is not implemented
using an emitter-follower topology, and therefore, a pull-down
resistor is not needed (and should be avoided) on the output pins.
Rather, it uses a CMOS output driver whose output amplitude
and common-mode voltage are compatible with LVPECL speci-
fications. 100 Ω termination across the output pair is still
recommended.
The user has the option to disable (that is, tristate) either or both of
the pins for OUT1 and/or OUT2 via the mode control bits (see
Table 19 for the 001, 010, and 011 bit patterns). Alternatively,
the user can make both pins active (see Table 19, Bit Pattern 000)
to produce two single-ended CMOS output clocks at OUT1
and/or OUT2.
Table 19. Output Mode Control Bits
Mode Control Bits Logic Family
Pin Function of the
Output Driver
000 CMOS Both pins active
001 CMOS Positive pin active,
negative pin tristate
010 CMOS Positive pin tristate,
negative pin active
011 CMOS Both pins tristate
100 LVDS Both pins active
101 LVPECL Both pins active
110 Unused Unused
111 Unused Unused
Note that the pin decoder for the OM2 to OM0 pins generates
two sets of mode control bits: one set for the OUT1 driver and
another set for the OUT2 driver. The relationship between the
logic levels applied to the OM2 to OM0 pins and the resulting
mode control bits appears in Table 20.
Table 20. OM2 to OM0 Pin Decoder
Pin OM2 to
Pin OM0
Mode Control Bits
OUT1 OUT2
000 101 101
001 101 100
010 100 101
011 101 001
100 100 100
101 100 001
110 001 100
111 001 001
This decoding scheme allows the OM2 to OM0 pins to establish a
matrix of logic family selections for the OUT1 and OUT2 drivers as
shown in Table 21
. Note that when the OM2 to OM0 pins select the
CMOS logic family, the signal at the
OUT1
pin is a phase aligned
replica of the signal at the OUT1 pin and the signal at the
OUT2
pin is a phase aligned replica of the signal at the OUT2 pin.
Table 21. Logic Family Assignment via the OM2 to OM0 Pins
Pin OM2 to
Pin OM0
Logic Family
OUT1 OUT2
000 LVPECL LVPECL
001 LVPECL LVDS
010 LVDS LVPECL
011 LVPECL CMOS
100 LVDS LVDS
101 LVDS CMOS
110 CMOS LVDS
111 CMOS CMOS