Datasheet

ManualsBrandsANALOG DEVICES ManualsClock & Timing ICsLFCSP 32 WQ

Flexible Clock Translator for GPON, Base

Station, SONET/SDH, T1/E1, and Ethernet

AD9553

Rev. A

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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FEATURES

Input frequencies from 8 kHz to 710 MHz

Output frequencies up to 810 MHz LVPECL and LVDS (up to

200 MHz for CMOS output)

Preset pin-programmable frequency translation ratios cover

popular wireline and wireless frequency applications,

including xDSL, T1/E1, BITS, SONET, and Ethernet

Arbitrary frequency translation ratios via SPI port

On-chip VCO

Accepts a crystal resonator for holdover applications

Two single-ended (or one differential) reference input(s)

Two output clocks (independently programmable as LVDS,

LVPECL, or CMOS)

SPI-compatible, 3-wire programming interface

Single supply (3.3 V)

Very low power: <450 mW (under most conditions)

Small package size (5 mm × 5 mm)

Exceeds Telcordia GR-253-CORE jitter generation, transfer,

and tolerance specifications

APPLICATIONS

Cost effective replacement of high frequency VCXO, OCXO,

and SAW resonators

Extremely flexible frequency translation for SONET/SDH,

Ethernet, Fibre Channel, DRFI/DOCSIS, and

PON/EPON/GPON

Wireless infrastructure

Test and measurement (including handheld devices)

GENERAL DESCRIPTION

The AD9553 is a phase-locked loop (PLL) based clock translator

designed to address the needs of passive optical networks (PON)

and base stations. The device employs an integer-N PLL to

accommodate the applicable frequency translation requirements.

The user supplies up to two single-ended input reference signals or

one differential input reference signal via the REFA and REFB

inputs. The device supports holdover applications by allowing the

user to connect a 25 MHz crystal resonator to the XTAL input.

The AD9553 is pin programmable, providing a matrix of standard

input/output frequency translations from a list of 15 possible input

frequencies to a list of 52 possible output frequency pairs (OUT1

and OUT2). The device also has a 3-wire SPI interface, enabling

the user to program custom input-to-output frequency translations.

The AD9553 output drivers are compatible with LVPECL, LVDS,

or single-ended CMOS logic levels, although the AD9553 is

implemented in a strictly CMOS process.

The AD9553 operates over the extended industrial temperature

range of −40°C to +85°C.

BASIC BLOCK DIAGRAM

PLL

OUTPUT

CIRCUITRY

INPUT

FREQUENCY

SOURCE

SELECTOR

REFA

REFB

XTAL

OUT2

OUT1

PIN-DEFINED AND SERIAL PROGRAMMING

AD9553

08565-001

Figure 1.

Summary of content (44 pages)

PAGE 1
Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet AD9553 FEATURES GENERAL DESCRIPTION Input frequencies from 8 kHz to 710 MHz Output frequencies up to 810 MHz LVPECL and LVDS (up to 200 MHz for CMOS output) Preset pin-programmable frequency translation ratios cover popular wireline and wireless frequency applications, including xDSL, T1/E1, BITS, SONET, and Ethernet Arbitrary frequency translation ratios via SPI port On-chip VCO Accepts a crystal resonator for holdover appli
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AD9553 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Overview ..................................................................................... 16 General Description ..............................................................
PAGE 3
AD9553 SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD = 3.3 V; TA = 25°C, unless otherwise noted. POWER CONSUMPTION Table 1. Parameter SUPPLY VOLTAGE TOTAL CURRENT Min 3.135 Typ 3.30 162 Max 3.
PAGE 4
AD9553 RESET PIN Table 4. Parameter INPUT CHARACTERISTICS1 Input Voltage High, VIH Input Voltage Low, VIL Input Current High, IINH Input Current Low, IINL MINIMUM PULSE WIDTH LOW 1 Min Typ Max Unit Test Conditions/Comments 0.3 31 0.85 12.5 43 V V µA µA µs Tested with an active source driving the RESET pin Max Unit Test Conditions/Comments 250 710 MHz MHz 769 mV 1.96 150 The RESET pin has a 100 kΩ internal pull-up resistor. REFERENCE CLOCK INPUT CHARACTERISTICS Table 5.
PAGE 5
AD9553 VCO CHARACTERISTICS Table 6. Parameter FREQUENCY RANGE VCO GAIN VCO TRACKING RANGE VCO CALIBRATION TIME Min 3350 Typ Max 4050 45 ±300 Unit MHz MHz/V ppm Test Conditions/Comments As measured from completion of the VCO calibration command (the rising edge of CS (Pin 12)) until the rising edge of LOCKED (Pin 20) Applies for Pin A3 to Pin A0 = 0001 to 1100, or for Pin A3 to Pin A0 = 1111 Low Bandwidth Setting (170 Hz) 13.
PAGE 6
AD9553 OUTPUT CHARACTERISTICS Table 8. Parameter LVPECL MODE Differential Output Voltage Swing Common-Mode Output Voltage Frequency Range Duty Cycle Rise/Fall Time1 (20% to 80%) Min Typ Max Unit Test Conditions/Comments 690 800 890 mV VDD − 1.66 0 40 VDD − 1.34 VDD − 1.
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AD9553 JITTER CHARACTERISTICS Table 9. Parameter JITTER GENERATION 12 kHz to 20 MHz LVPECL Output LVDS Output CMOS Output 50 kHz to 80 MHz LVPECL Output LVDS Output CMOS Output JITTER TRANSFER BANDWIDTH Low Bandwidth Setting Medium Bandwidth Setting High Bandwidth Setting JITTER TRANSFER PEAKING Low BW Setting Medium BW Setting High BW Setting Min Typ Max Unit Test Conditions/Comments 1.28 0.89 ps rms ps rms 1.31 1.29 1.32 1.26 ps rms ps rms ps rms ps rms 1.24 ps rms Input = 19.
PAGE 8
AD9553 SERIAL CONTROL PORT Table 10. Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO Input Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance Output Output Logic 1 Voltage Output Logic 0 Voltage Min Typ Max 1.6 0.5 0.03 2 2 1.6 0.5 2 0.03 2 1.6 0.5 1 1 2 2.8 0.
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AD9553 ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 12. Parameter Supply Voltage (VDD) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 3.6 V −0.5 V to VDD + 0.5 V −65°C to +150°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 10
AD9553 32 31 30 29 28 27 26 25 Y3 Y2 Y1 Y0 VDD OUT1 OUT1 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD9553 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 GND OUT2 OUT2 VDD LOCKED LDO VDD LDO NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND. 08565-002 XTAL XTAL SEL REFB OM2/CS OM1/SCLK OM0/SDIO RESET FILTER 9 10 11 12 13 14 15 16 Y4 Y5 A0 A1 A2 A3 REFA REFB/REFA Figure 2. Pin Configuration Table 13.
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AD9553 TYPICAL PERFORMANCE CHARACTERISTICS –30 –70 JITTER BANDWIDTH JITTER (rms) 12kHz TO 20MHz 1.30ps 50kHz TO 80MHz 0.62ps –40 –50 –90 PHASE NOISE (dBc/Hz) –60 PHASE NOISE (dBc/Hz) JITTER BANDWIDTH JITTER (rms) 12kHz TO 20MHz 0.73ps 50kHz TO 80MHz 0.
PAGE 12
AD9553 5 249 0 248 248.3MHz XTAL TO REF A TRANSITION JITTER TRANSFER +15.6MHz/ms 2 –10 –15 –20 –25 1 JITTER PEAKING 0 –1 –19.6MHz/ms 246 245 REF A TO XTAL TRANSITION 244 REF B TO A TRANSITION –2 REF A TO B TRANSITION 243 –3 25 50 75 100 125 150 175 FREQUENCY OFFSET (Hz) –30 10 242.8MHz 100 1k FREQUENCY OFFSET (Hz) 242 08565-028 0 0 2 4 6 8 10 12 14 16 18 20 TIME (ms) Figure 9.
PAGE 13
AD9553 1800 35 LVPECL 1600 LVPECL OUTPUT VOLTAGE (mV p-p) LVDS STRONG 25 20 LVDS WEAK 15 10 5 1400 1200 LVDS STRONG 1000 800 LVDS WEAK 600 400 200 0 100 200 300 400 500 600 700 800 900 FREQUENCY (MHz) 0 08565-209 0 0 100 200 300 400 500 600 700 800 900 FREQUENCY (MHz) Figure 15. Supply Current vs. Output Frequency, LVPECL and LVDS (10 pF Load) 08565-212 SUPPLY CURRENT (mA) 30 Figure 18. Peak-to-Peak Output Voltage vs.
PAGE 14
AD9553 2 500ps/DIV 500mV/DIV Figure 21. Typical Output Waveform, LVPECL (800 MHz) 500ps/DIV 08565-216 2 125mV/DIV 1.25ns/DIV Figure 23. Typical Output Waveform, CMOS (250 MHz, 10 pF Load) Figure 22. Typical Output Waveform, LVDS (800 MHz, 3.5 mA Drive Current) Rev.
PAGE 15
AD9553 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1µF 100Ω DOWNSTREAM DEVICE 0.1µF 0.1µF AD9553 SELF-BIASED REFERENCE INPUT 08565-326 Figure 24. AC-Coupled LVDS or LVPECL Output Driver Figure 26. Reference Input DOWNSTREAM DEVICE 08565-325 100Ω AD9553 3.3V DIFFERENTIAL OUTPUT (LVDS OR LVPECL MODE) (OPTIONAL) HIGH IMPEDANCE INPUT 08565-324 100Ω AD9553 3.3V DIFFERENTIAL OUTPUT (LVDS OR LVPECL MODE) 0.1µF Figure 25. DC-Coupled LVDS or LVPECL Output Driver Rev.
PAGE 16
AD9553 THEORY OF OPERATION FILTER LOCKED TEST SEL REFB 1 0 CLOCK MUX UP/2 FPFD/2 FDBK/2 XO HOLD REF DET DET DET SEL A B XO DET A REFA ×2 0 1 ÷5 REF DIFF 0 1 1 0 DET LOCK DETECT ×2A 3350MHz TO 4050MHz 5 TO 11 PLL ÷RA FPFD P F D RA UP CHARGE PUMP LOOP FILTER DN 3 ×2 REFB/REFA ÷5 0 1 1 0 DET XO XO DCXO CTRL XTAL TUNING CONTROL FDBK ÷RB ×2 P2 2 P1 P0 P1 OUTPUT MODE CONTROL 20 3 1 0 N RB DET ÷RXO 14 RXO OUT1 10 ÷N 14 ×2B ÷5B XTAL DET OUT2 10 P0 VCO HOLD DET B 2
PAGE 17
AD9553 The Ax pins allow the user to select one of fifteen input reference frequencies as shown in Table 14. The device sets the appropriate divide-by-5 (÷5A, ÷5B), multiply-by-2 (×2A, ×2B), and input divider (RA, RB, RXO) values based on the logic levels applied to the Ax pins. The same settings apply to both the REFA and REFB input paths. Furthermore, the ÷5, ×2, and R values cause the PLL input frequency to be either 16 kHz or 40/3 kHz. There are two exceptions.
PAGE 18
AD9553 Table 15. Pin Configured Output Frequency, Yx Pins Pin Y5 to Pin Y0 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 to 111110 111111 1 fVCO (MHz) fOUT1 (MHz) 3686.4 3686.4 3686.
PAGE 19
AD9553 Table 16. Pin Configuration vs.
PAGE 20
AD9553 SPI/OM[2:0] A[3:0] 3 1 3 6 4 FREQUENCY SELECTION PINS DECODER SPI MODE 0 Y[5:0] 3 OUTPUT MODE CONTROL DECODER SPI CONTROLLER 3 OUTPUT MODE CONTROL FUNCTION BITS ENABLE SPI CONTROL OF OUTPUT MODE 0 3 1 OUTPUT MODE CONTROL FUNCTION ENABLE SPI CONTROL OF OUTPUT ABC BITS FUNCTION ABC BITS 0 1 FUNCTION ABC ENABLE SPI CONTROL OF FUNCTIONING XYZ 0 1 FUNCTION MUXES REGISTER MAP FUNCTION XYZ 08565-100 FUNCTION XYZ BITS Figure 28.
PAGE 21
AD9553 of a fixed component of 8 pF and a variable (programmable) component of 0 pF to 15.75 pF. After applying power to the AD9553 (or after a device reset), the programmable component defaults to 2 pF. This establishes the default load capacitance of 10 pF (8 pF fixed plus 2 pF programmable). To accommodate crystals with a specified load capacitance other than 10 pF (8 pF to 23.75 pF), the user can adjust the programmable capacitance in 0.25 pF increments via Register 0x1B[5:0].
PAGE 22
AD9553 RA DIVIDER FROM REFA INPUT ÷ RB DIVIDER FROM REFB INPUT FROM XTAL INPUT TO PLL ÷ RXO DIVIDER ÷ CLOCK MUX XTAL PRESENT SIGNAL REFB PRESENT DETECTOR REFA PRESENT FDBK MUX CONTROL LOGIC 11 SEL REFB REG 0x29[7:6] 00 NON-REVERTIVE 01 SELECT REFA 10 SELECT REFB 11 SEL B/A REVERTIVE/ NON-REVERTIVE LOGIC SEL B/A SPI SELECT REFA/B LOGIC SEL B/A SEL B/A REFA/B SELECTION LOGIC 08565-102 REVERTIVE Figure 29.
PAGE 23
AD9553 Loop Filter Alternatively, the LOCKED pin serves as a test port allowing the user to monitor one-of-four internal clocks. Register 0x17[3:1] controls the test port as shown in Table 18. The charge pump in the PFD delivers current to the loop filter (see Figure 30). The components primarily responsible for the bandwidth of the loop filter are external and connect between Pin 16 and Pin 17. Table 18.
PAGE 24
AD9553 The mode control bits establish the logic family and output pin function of the associated output driver per Table 19. The logic families include LVDS, LVPECL, and CMOS. Because both output drivers support the LVDS and LVPECL logic families, each driver has two pins to handle the differential signals associated with these two logic families. The OUT1 driver uses the OUT1 and OUT1 pins and the OUT2 driver uses the OUT2 and OUT2 pins.
PAGE 25
AD9553 REGISTER 0x32 BITS [5:3] BIT 0 BIT 7 0 1 101 BIT 6 0 DRIVE STRENGTH MODE CONTROL BITS [2:1] 00 POWER- CMOS DOWN POLARITY ENABLE SPI CONTROL 2 3 REGISTER DEFAULT VALUES SHOWN IN RED 3 1 3 OUTPUT CONTROL 0 OM[2:0] 3 PIN DECODE LOGIC 2 DRIVER 3 OUT1 MODE CONTROL 3 2 DRIVER OUT2 3 0 OUTPUT CONTROL 3 1 2 ENABLE SPI CONTROL DRIVE STRENGTH 101 BITS [5:3] 0 BIT 0 POWER- CMOS DOWN POLARITY 1 BIT 7 0 BIT 6 00 BITS [2:1] REGISTER 0x34 08565-104 MODE CONTROL Figure 31.
PAGE 26
AD9553 JITTER TOLERANCE Jitter tolerance is the ability of the AD9553 to maintain lock in the presence of sinusoidal jitter. The AD9553 meets the input jitter tolerance mask per Telcordia GR-253-CORE (see Figure 32). The acceptable jitter tolerance is the region above the mask. The trace showing the performance of the AD9553 in Figure 32 represents the limitations of the test equipment because the AD9553 did not indicate loss of lock, even with the test equipment injecting its maximum jitter level.
PAGE 27
AD9553 Generally, the AD9553 is for applications in which fREFA and fREFB are the same frequency, so the multiplexers in the REFA and REFB paths share identical configurations. This, in conjunction with the crystal frequency (fXTAL), results in the following relationship between the RA and RXO dividers (here K is the scale factor for the REFA path). 2 × f XTAL R = K × XO f REFA RA 3. (1) Note that for pin programmed holdover applications using the crystal, the crystal frequency must be 25 MHz.
PAGE 28
AD9553 6. Determine N, K, and R. For fVCO = 3888 MHz, an obvious solution is K = 1, R = 125, and N = 3888, which satisfies the constraint on both N and R, and yields FPFD = 1 MHz. If applicable, determine RXO, the XTAL divider value. The value of RXO depends on the value of fREF, K, and R from Step 5, as follows:  50 × 10 6 R XO =   f REF For fVCO = 3732.48 MHz, an obvious solution is N = 373,248, K = 1, and R = 12,500. This choice, however, violates the constraints on both N and R in Step 3.
PAGE 29
AD9553 APPLICATIONS INFORMATION THERMAL PERFORMANCE The AD9553 is specified for case temperature (TCASE). To ensure that TCASE is not exceeded, use an airflow source. Use the following equation to determine the junction temperature on the application printed circuit board (PCB): TJ = TCASE + (ΨJT × PD) Values of θJA are provided for package comparison and PCB design considerations.
PAGE 30
AD9553 SERIAL CONTROL PORT The AD9553 serial control port is a flexible, synchronous, serial communications port that allows an easy interface to many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9553 serial control port is configured for a single bidirectional I/O pin (SDIO only).
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AD9553 MSB/LSB FIRST TRANSFERS OM0/SDIO 14 OM2/CS SERIAL CONTROL PORT 12 REGISTER UPDATE EXECUTE AN INPUT/OUTPUT UPDATE The AD9553 instruction word and byte data can be MSB first or LSB first. The default for the AD9553 is MSB first. The LSB first mode can be set by writing a 1 to Register 0x00[6] and requires that an I/O update be executed. Immediately after the LSB first bit is set, all serial control port operations are changed to LSB first order.
PAGE 32
AD9553 CS SCLK DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A1 A0 A4 A3 A2 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D6 D5 D7 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 08565-008 SDIO DON'T CARE DON'T CARE Figure 36.
PAGE 33
AD9553 REGISTER MAP A bit that is labeled ACLR is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns it to a Logic 0 state upon completion of the indicated task. Table 27. Register Map Addr.
PAGE 34
AD9553 Addr.
PAGE 35
AD9553 REGISTER MAP DESCRIPTIONS Control bit functions are active high unless stated otherwise. Register address values are always hexadecimal unless otherwise indicated. Serial Port Control (Register 0x00 to Register 0x05) Table 28. Address 0x00 0x04 0x05 Bit 7 6 Bit Name Unused LSB first 5 4 Soft reset Unused [3:0] [7:1] 0 Unused Unused Readback control [7:1] 0 Unused I/O update Description Forced to Logic 0 internally, which enables 3-wire mode only. Bit order for SPI port.
PAGE 36
AD9553 Address 0x0C Bit [7:3] [2:0] Bit Name Unused Charge pump clock div. 0x0D [7:6] Antibacklash control [5:1] 0 Unused PLL lock detector power-down Description Unused. Enables the PFD clock dividers (used for test only via test mux). 000 = test clocks disabled, normal operation (default). 001 = divide feedback clock by 2. 010 = divide PFD reference input clock by 2. 011 = divide PFD reference input and feedback clocks by 2. 100 = divide pump-up clock by 2.
PAGE 37
AD9553 PLL and Output Frequency Control (Register 0x11 to Register 0x19) Table 31.
PAGE 38
AD9553 Input Receiver and Band Gap Control (Register 0x1A) Table 32. Address 0x1A Bit 7 Bit Name Receiver reset [6:2] Band gap voltage adjust 1 0 Unused Enable SPI control of band gap voltage Description Input receiver reset control. This is an autoclearing bit. 0 = normal operation (default). 1 = resets the reference input hardware (detectors, dividers, switchover control, crystal oscillator, and its associated frequency doubler).
PAGE 39
AD9553 REFB Frequency Control (Register 0x23 to Register 0x26) Table 35. Address 0x23 0x24 0x25 0x26 Bit [7:0] [7:2] Bit Name REFB divider (RB) REFB divider (RB) 1 Enable SPI control of RB 0 7 Unused Enable SPI control of ×2B 6 Select ×2B 5 Enable SPI control of ÷5B 4 Select ÷5B [3:0] [7:0] Unused Unused Description Bits[13:6] of the 14-bit REFB divider. Bits[5:0] of the 14-bit REFB divider (default: RB = 8192 decimal). The REFB divider bits are ineffective unless Register 0x24[1] = 1.
PAGE 40
AD9553 OUT1 Driver Control (Register 0x32) Table 37. Address 0x32 Bit 7 Bit Name OUT1 drive strength 6 OUT1 power-down [5:3] OUT1 mode control 2 OUT1 CMOS polarity 1 0 OUT1 mode source Unused Description Controls the output drive capability of the OUT1 driver. 0 = weak. 1 = strong (default). Controls power-down functionality of the OUT1 driver. 0 = OUT1 active (default). 1 = OUT1 powered down. OUT1 driver mode selection. 000 = CMOS, both pins active.
PAGE 41
AD9553 OUT2 Driver Control (Register 0x34) Table 39. Address 0x34 Bit 7 Bit Name OUT2 drive strength 6 OUT2 power-down [5:3] OUT2 mode control 2 OUT2 CMOS polarity 1 0 OUT1 mode source Unused Description Controls the output drive capability of the OUT2 driver. 0 = weak. 1 = strong (default). Controls power-down functionality of the OUT2 driver. 0 = OUT2 active (default). 1 = OUT2 powered down. OUT2 driver mode selection. 000 = CMOS, both pins active.
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AD9553 OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 42.
PAGE 43
AD9553 NOTES Rev.