Datasheet

AD9552 Data Sheet
Rev. E | Page 6 of 32
SERIAL CONTROL PORT
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
CS
Input Logic 1 Voltage 1.6 V
Input Logic 0 Voltage 0.5 V
Input Logic 1 Current 0.03 µA
Input Logic 0 Current 2 µA
Input Capacitance 2 pF
SCLK
Input Logic 1 Voltage 1.6 V
Input Logic 0 Voltage 0.5 V
Input Logic 1 Current 2 µA
Input Logic 0 Current 0.03 µA
Input Capacitance 2 pF
SDIO
Input
Input Logic 1 Voltage 1.6 V
Input Logic 0 Voltage 0.5 V
Input Logic 1 Current 1 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
Output
Output Logic 1 Voltage 2.8 V 1 mA load current
Output Logic 0 Voltage 0.3 V 1 mA load current
SERIAL CONTROL PORT TIMING
Table 6.
Parameter
Limit
Unit
SCLK
Clock Rate, 1/t
CLK
50 MHz max
Pulse Width High, t
HIGH
3 ns min
Pulse Width Low, t
LOW
3 ns min
SDIO to SCLK Setup, t
DS
4 ns min
SCLK to SDIO Hold, t
DH
0 ns min
SCLK to Valid SDIO, t
DV
13 ns max
CS
to SCLK Setup (t
S
) and Hold (t
H
) 0 ns min
CS
Minimum Pulse Width High
6.4
ns min