Datasheet
Data Sheet AD9552
Rev. E | Page 3 of 32
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD = 3.3 V; T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE
3.135
3.30
3.465
V
Pin 7, Pin 18, Pin 21, Pin 28
POWER CONSUMPTION
Total Current 149 169 mA At maximum output frequency with both output channels active
VDD Current By Pin
Pin 7 2 3 mA
Pin 18 77 86 mA
Pin 21 35 41 mA
Pin 28 35 41 mA
LVPECL Output Driver 36 41 mA 900 MHz with 100 Ω termination between both pins of the output
driver
LOGIC INPUT PINS
INPUT CHARACTERISTICS
1
Logic 1 Voltage, V
IH
1.0 V For the CMOS inputs, a static Logic 1 results from either a pull-up
resistor or no connection
Logic 0 Voltage, V
IL
0.8 V
Logic 1 Current, I
IH
3 µA
Logic 0 Current, I
IL
17 µA
LOGIC OUTPUT PINS
Output Characteristics
Output Voltage High, V
OH
2.7 V
Output Voltage Low, V
OL
0.4 V
RESET PIN
Input Characteristics
2
Input Voltage High, V
IH
1.8 V
Input Voltage Low, V
IL
1.3 V
Input Current High, I
INH
0.3 12.5 µA
Input Current Low, I
INL
31 43 µA
Minimum Pulse Width High 2 ns
REFERENCE CLOCK
INPUT CHARACTERISTICS
Frequency Range 7.94 MHz N
3
= 255; 2× frequency multiplier enabled; valid for all VCO bands
6.57 MHz N
3
= 255; 2× frequency multiplier enabled; f
VCO
= 3.35 GHz, which con-
strains the frequency at OUT1 to be an integer sub-multiple of 3.35 GHz
(that is, f
OUT1
= 3.35 ÷ M GHz, where M is the product of the P
0
and P
1
output divider values)
93.06 MHz SDM
4
disabled; N
3
= 36
5
; valid for all VCO bands
71.28
MHz
SDM
4
enabled; N
3
= 47
6
; valid for all VCO bands
112.5 MHz SDM
4
disabled; N
3
= 36
5
; f
VCO
= 4.05 GHz, which constrains the
frequency at OUT1 to be an integer sub-multiple of 4.05 GHz (that is,
f
OUT1
= 4.05÷M GHz, where M is the product of the P
0
and P
1
output
divider values)
86.17 MHz SDM
4
enabled; N
3
= 47
6
; f
VCO
= 4.05 GHz, which constrains the frequency
at OUT1 to be an integer sub-multiple of 4.05 GHz (that is, f
OUT1
=
4.05÷M GHz, where M is the product of the P
0
and P
1
output divider
values)