Datasheet
Data Sheet AD9552
Rev. E | Page 23 of 32
REGISTER MAP
A bit that is labeled “aclr” is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns it to a
Logic 0 state upon completion of the indicated task.
Table 17. Register Map
Addr.
(Hex)
Register
Name
(MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
0x00 Serial port
control
0 LSB first Register
map reset
(aclr)
1 1 Register
map reset
LSB first 0 0x18
0x04 Readback
control
Unused Unused Unused Unused Unused Unused Unused Readback
control
0x00
0x05
I/O update
Unused
Unused
Unused
Unused
Unused
Unused
Unused
I/O update
(aclr)
0x00
0x0A PLL charge
pump and
PFD
control
Charge pump current control[7:0]
(3.5 µA granularity, ~900 µA full scale)
0x80
0x0B PLL charge
pump and
PFD
control
Enable SPI
control of
charge
pump
current
Enable SPI
control of
antiback-
lash
period
CP mode[1:0] Enable CP
mode
control
PFD
feedback
input edge
control
PFD
reference
input edge
control
Force VCO
to
midpoint
frequency
0x30
0x0C PLL charge
pump and
PFD
control
Unused CP offset
current
polarity
CP offset current[1:0] Enable CP
offset
current
control
Reserved Reserved Reserved 0x00
0x0D PLL charge
pump and
PFD
control
Antibacklash control[1:0] Unused Unused Unused Unused Unused PLL lock
detector
power-
down
0x00
0x0E VCO
control
Calibrate
VCO (aclr)
Enable
ALC
ALC threshold[2:0] Enable SPI
control of
VCO
calibration
Boost VCO
supply
Enable SPI
control of
VCO band
setting
0x70
0x0F VCO
control
VCO level control[5:0] Unused Unused 0x80
0x10 VCO
control
VCO band control[6:0] Unused 0x80
0x11 PLL control N[7:0] (SDM integer part) 0x00
0x12
PLL control
MOD[19:12] (SDM modulus)
0x80
0x13 PLL control MOD[11:4] (SDM modulus) 0x00
0x14 PLL control MOD[3:0] (SDM modulus) Enable SPI
control of
output
frequency
Bypass
SDM
Disable SDM Reset PLL 0x00
0x15 PLL control FRAC[19:12] (SDM fractional part) 0x20
0x16 PLL control FRAC[11:4] (SDM fractional part) 0x00
0x17 PLL control FRAC[3:0] (SDM fractional part) Unused Unused Unused P
1
divider[5] 0x01
0x18
PLL control
P
1
divider[4:0]
P
0
divider[2:0]
0x00
0x19 PLL control Enable SPI
control
of OUT1
dividers
Unused Unused 0x20
0x1A Input
receiver and
band gap
Receiver
reset (aclr)
Band gap voltage adjust[4:0]
(00000 = maximum, 11111 = minimum)
Unused Enable SPI
control of
band gap
voltage
0x00
0x1B
XTAL
tuning
control
Disable SPI
control of
XTAL tuning
Unused
XTAL tuning capacitor control[5:0]
(0.25 pF per bit, inverted binary coding)
0x80