Datasheet

AD9549
Rev. D | Page 8 of 76
Parameter Min Typ Max Unit Test Conditions/Comments
LOCK DETECTION
Phase Lock Detector
Time Threshold Programming Range 0 2097 μs FPFD_gain = 200
Time Threshold Resolution 0.488 ps FPFD_gain = 200
Lock Time Programming Range 32 × 10
−9
275 sec In power-of-2 steps
Unlock Time Programming Range 192 ×
10
−9
67 × 10
−3
sec In power-of-2 steps
Frequency Lock Detector
Normalized Frequency Threshold
Programming Range
0 0.0021 FPFD_gain = 200; normalized to (f
REF
/R)
2
; see the
Frequency Lock Detection section for details
Normalized Frequency Threshold
Programming Resolution
5 ×
10
−13
FPFD_gain = 200; normalized to (f
REF
/R)
2
; see the
Frequency Lock Detection section for details
Lock Time Programming Range 32 × 10
−9
275 sec In power-of-2 steps
Unlock Time Programming Range 192 ×
10
−9
67 × 10
−3
sec In power-of-2 steps
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down 15 µs
Time Required to Leave Power-Down 18 µs
Reset Assert to High-Z Time
for S1 to S4 Configuration Pins
60 ns Time from rising edge of RESET to high-Z on the S1,
S2, S3, and S4 configuration pins
Reset Deassert to Low-Z Time
for S1 to S4 Configuration Pins
30 ns Time from falling edge of RESET to low-Z on the S1, S2,
S3, and S4 configuration pins
SERIAL PORT TIMING SPECIFICATIONS
SCLK Clock Rate (1/t
CLK
) 25 50 MHz
Refer to
Figure 58 for all write-related serial port
parameters, maximum SCLK rate for readback is
governed by t
DV
SCLK Pulse Width High, t
HIGH
8 ns
SCLK Pulse Width Low, t
LOW
8 ns
SDO/SDIO to SCLK Setup Time, t
DS
1.93 ns
SDO/SDIO to SCLK Hold Time, t
DH
1.9 ns
SCLK Falling Edge to Valid Data on
SDIO/SDO, t
DV
11 ns
Refer to
Figure 56
CSB to SCLK Setup Time, t
S
1.34 ns
CSB to SCLK Hold Time, t
H
−0.4 ns
CSB Minimum Pulse Width High, t
PWH
3 ns
IO_UPDATE Pin Setup Time
from SCLK Rising Edge of the Final Bit
t
CLK
sec t
CLK
= period of SCLK in Hz
IO_UPDATE Pin Hold Time t
CLK
sec t
CLK
= period of SCLK in Hz
PROPAGATION DELAY
FDBK_IN to HSTL Output Driver 2.8 ns
FDBK_IN to HSTL Output Driver with 2×
Frequency Multiplier Enabled
7.3 ns
FDBK_IN to CMOS Output Driver 8.0 ns
FDBK_IN Through S-Divider to CMOS
Output Driver
8.6 ns
Frequency Tuning Word Update,
IO_UPDATE Pin Rising Edge to DAC
Output
60/fs ns fs = system clock frequency in GHz