Datasheet

AD9549
Rev. D | Page 71 of 76
Register 0x0406—Part Version
Table 127.
Bits Bit Name Description
[7:6] Part version 01b = AD9549, Revision A
00b = AD9549, Revision 0
[5:0] Reserved N/A
Register 0x0407 to Register 0x0408—Reserved
Register 0x0409—PFD Offset
Table 128.
Bits Bit Name Description
[7:0] DPLL phase offset This register controls the static time offset of the PFD (phase frequency detector) in closed-loop mode.
It has no effect when the DPLL is open.
Register 0x040A—PFD Offset (Continued)
Table 129.
Bits Bit Name Description
[13:8] DPLL phase offset This register controls the static time offset of the PFD (phase frequency detector) in closed-loop mode.
It has no effect when the DPLL is open.
Register 0x040B—DAC Full-Scale Current
Table 130.
Bits Bit Name Description
[7:0] DAC full-scale current DAC full-scale current, Bits[7:0]. See the DAC Output section.
Register 0x040C—DAC Full-Scale Current (Continued)
Table 131.
Bits Bit Name Description
[9:8] DAC full-scale current DAC full-scale current, Bits[9:8]. See Register 0x040B.
Register 0x040D to Register 0x040E—Reserved
Register 0x040F—Reference Bias Level
Table 132.
Bits Bit Name Description
[7:2] Reserved Reserved.
[1:0] DC input level This register sets the dc bias level for the reference inputs. The value should be chosen such that V
IH
is
as close as possible to, but does not exceed, 3.3 V.
00 = VDD3 − 800 mV.
01 = VDD3 − 400 mV.
10 = VDD3 − 1.6 V.
11 = VDD3 − 1.2 V.
Register 0x0410—Reserved
HARMONIC SPUR REDUCTION (REGISTER 0x0500 TO REGISTER 0x0509)
See the Harmonic Spur Reduction section.