Datasheet

AD9549
Rev. D | Page 7 of 76
Parameter Min Typ Max Unit Test Conditions/Comments
CMOS Output Driver
(AVDD3/Pin 37) @ 3.3 V
Frequency Range 0.008 150 MHz
See
Figure 14 for maximum toggle rate
Duty Cycle 45 55 65 % With 20 pF load and up to 150 MHz
Rise Time/Fall Time (20-80%) 3 4.6 ns With 20 pF load
CMOS Output Driver
(AVDD3/Pin 37) @ 1.8 V
Frequency Range 0.008 40 MHz
See
Figure 13 for maximum toggle rate
Duty Cycle 45 55 65 % With 20 pF load and up to 40 MHz
Rise Time/Fall Time (20% to 80%) 5 6.8 ns With 20 pF load
HOLDOVER
Frequency Accuracy
See the
Holdover section
OUTPUT FREQUENCY SLEW LIMITER
Slew Rate Resolution 0.54 111 Hz/sec P = 2
16
for minimum; P = 2
5
for maximum
Slew Rate Range 0 3 × 10
16
Hz/sec P = 2
16
for minimum; P = 2
5
for maximum
REFERENCE MONITORS
Loss of Reference Monitor
Operating Frequency Range 7.63 × 10
3
167 × 10
6
Hz
Minimum Frequency Error for
Continuous REF Present Indication
−16 ppm f
REF
= 8 kHz
Minimum Frequency Error for
Continuous REF Present Indication
−19 % f
REF
= 155 MHz
Maximum Frequency Error for
Continuous REF Lost Indication
−32 ppm f
REF
= 8 kHz
Maximum Frequency Error for
Continuous REF Lost Indication
−35 % f
REF
= 155 MHz
Reference Quality Monitor
Operating Frequency Range 0.008 150 MHz
Frequency Resolution (Normalized) 0.2 ppm f
REF
= 8 kHz; OOL divider = 65,535 for minimum; OOL
divider = 1 for max (see the
Reference Frequency
Monitor
section)
Frequency Resolution (Normalized) 408 ppm f
REF
= 155 MHz; OOL divider = 65,535 for minimum;
OOL divider = 1 for maximum
Validation Timer
See the
Reference Validation Timers section
Timing Range 32 × 10
−9
137 sec P
IO
= 5
Timing Range 65 × 10
−6
2.8 × 10
5
sec P
IO
= 16
DAC OUTPUT CHARACTERISTICS
DCO Frequency Range (1
st
Nyquist Zone) 10 450 MHz DPLL loop bandwidth sets lower limit
Output Resistance 50 Ω Single-ended (each pin internally terminated to AVSS)
Output Capacitance 5 pF
Full-Scale Output Current 20 31.7 mA Range depends on DAC R
SET
resistor
Gain Error −10 +10 % FS
Output Offset 0.6 μA
Voltage Compliance Range AVSS −
0.50
+0.5 AVSS +
0.50
Outputs not dc-shorted to V
SS
DIGITAL PLL
Minimum Open-Loop Bandwidth 0.1 Hz Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Maximum Open-Loop Bandwidth 100 kHz Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Minimum Phase Margin 0 10 Degrees Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Maximum Phase Margin 85 90 Degrees Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
PFD Input Frequency Range ~0.008 ~24.5 MHz
Feedforward Divider Ratio 1 131,070 1, 2, …, 65,535 or 2, 4, …, 131,070
Feedback Divider Ratio 1 131,070 1, 2, …, 65,535 or 2, 4, …, 131,070