Datasheet
AD9549
Rev. D | Page 55 of 76
Register 0x0023—PFD Divider
Table 22.
Bits Bit Name Description
[3:0] PFD divider Divide ratio for PFD clock from system clock. This is typically varied only in cases where the designer wishes
to run the DPLL phase detector fast while SYSCLK is run relatively slowly. The ratio is equal to PFD
divider × 4. For a 1 GHz system clock, the ADC runs at 1 GHz/20 = 50 MHz, and the DPLL phase detector
runs at half this speed, which, in this case, is 25 MHz.
DIGITAL PLL CONTROL AND DIVIDERS (REGISTER 0x0100 TO REGISTER 0X0130)
Register 0x0100—PLL Control
Table 23.
Bits Bit Name Description
[7:6] Reserved Reserved
5 Single-tone mode Setting this bit allows the AD9549 to output a tone open loop using FTW0 as DDS tuning word. This bit
must be cleared when Bit 0 (close loop) is set. This is very useful in debugging when the signal coming
into the AD9549 is questionable or nonexistent.
4 Disable frequency
estimator
The frequency estimator is normally not used but is useful when the input frequency is unknown or
needs to be qualified. This estimate appears in Register 0x0115 to Register 0x011A. The frequency
estimator is not needed when FTW0 (Register 0x01A6 to Register 0x01AB) is programmed. See the
Frequency Estimator section.
3 Enable frequency slew
limiter
This bit enables the frequency slew limiter that controls how fast the tuning word can change and is
useful for avoiding runt and stretched pulses during clock switchover and holdover transitions. These
values are set in Register 0x0127 to Register 0x012C. See the Frequency Slew Limiter section.
2 Reserved Reserved.
1 Loop polarity This bit reverses the polarity of the loop response.
0 Close loop Setting this bit closes the loop. If Bit 4 of this register is cleared, the frequency estimator is used. If this
bit is cleared and the loop is opened, reset the CCI and LF bits of Register 0x0012 before closing the
loop again. A valid input reference signal must be present the first time the loop is closed. If no input
signal is present during the first time the loop is closed, the user must reset the digital PLL blocks by
writing 0xFF to Register 0x0012 before attempting to close the loop again.
Register 0x0101—R-Divider (DPLL Feedforward Divider)
Table 24.
Bits Bit Name Description
[7:0] R-divider Feedforward divider (also called the reference divider) of the DPLL. Divide ratio = 1 − 65,536. See the
Feedforward Divider (Divide-by-R) section. If the desired feedforward ratio is greater than 65,536, or if
the reference input signal on REFA or REFB is greater than 400 MHz, Bit 0 of Register 0x0103 must be
set. Note that the actual R-divider is the value in this register plus 1; to have an R-divider of 1, Register
0x0101 and Register 0x0102 must both be 0x00. Register 0x0101 is the least significant byte.
Register 0x0102—R-Divider (DPLL Feedforward Divider) (Continued)
Table 25.
Bits Bit Name Description
[15:8] R-divider Feedforward divider (also called the reference divider) of the DPLL. Divide ratio = 1 − 65,536. See the
Feedforward Divider (Divide-by-R) section. If the desired feedforward ratio is greater than 65,536, or if
the reference input signal on REFA or REFB is greater than 400 MHz, Bit 0 of Register 0x0103 must be
set. Note that the actual R-divider is the value in this register plus 1; to have an R-divider of 1, Register
0x0101 and Register 0x0102 must both be 0x00. Register 0x0101 is the least significant byte.
Register 0x0103—R-Divider (Continued)
Table 26.
Bits Bit Name Description
7 Falling edge triggered Setting this bit inverts the reference clock before the R-divider.
[6:1] Reserved Reserved.
0 R-divider/2 Setting this bit enables an additional /2 prescaler, effectively doubling the range of the feedforward
divider. If the desired feedforward ratio is greater than 65,536, or if the reference input signal on REFA or
REFB is greater than 400 MHz, then this bit must be set.