Datasheet

AD9549
Rev. D | Page 14 of 76
06744-009
10 30 50 70 90
SYSTEM CLOCK PLL INPUT FREQUENCY (MHz)
2.0
1.5
1.0
0.5
0
12kHz TO 20MHz RMS JITTER (ps)
Figure 9. 12 kHz to 20 MHz RMS Jitter vs. System Clock PLL Input Frequency,
SYSCLK = 1 GHz, f
REF
= 19.44 MHz, f
OUT
= 155.52 MHz
06744-010
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PHASE NOISE (dBc/Hz)
RMS JITTER (12kHz TO 20MHz): 1.26ps
RMS JITTER (50kHz TO 80MHz): 1.30ps
Figure 10. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by a 25 MHz Fox Crystal Oscillator),
f
REF
= 19.44 MHz, f
OUT
= 155.52 MHz, DPLL Loop BW = 1 kHz
06744-011
10 100 1k 10k 100k 1M 10M
FREQ
UENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PHASE NOISE (dBc/Hz)
RMS JITTER (12kHz TO 20MHz): 4.2ps
Figure 11. Additive Phase Noise at HSTL Output Driver, SYSCLK = 500 MHz
(SYSCLK PLL Disabled), f
REF
= 10.24 MHz, f
OUT
= 20.48 MHz,
DPLL Loop BW = 1 kHz