Datasheet

AD9549
Rev. D | Page 13 of 76
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, AVDD, AVDD3, and DVDD are at nominal supply voltage; f
S
= 1 GHz, DAC R
SET
= 10 kΩ.
06744-003
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PHASE NOISE (dBc/Hz)
RMS JITTER (12kHz TO 20MHz): 0.18ps
RMS JITTER (50kHz TO 80MHz): 0.24ps
Figure 3. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Bypassed), f
REF
= 19.44 MHz,
f
OUT
= 311.04 MHz, DPLL Loop BW = 1 kHz
06744-004
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PHASE NOISE (dBc/Hz)
RMS JITTER (12kHz TO 20MHz): 0.36ps
RMS JITTER (50kHz TO 80MHz): 0.42ps
Figure 4. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Bypassed), f
REF
= 19.44 MHz, f
OUT
= 622.08 MHz,
DPLL Loop BW = 1 kHz, HSTL Output Doubler Enabled
06744-005
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PHASE NOISE (dBc/Hz)
RMS JITTER (12kHz TO 20MHz): 1.01ps
RMS JITTER (50kHz TO 80MHz): 1.04ps
Figure 5. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled Driven by R&S SMA100 Signal Generator at 50 MHz),
f
REF
= 19.44 MHz, f
OUT
= 311.04 MHz, DPLL Loop BW = 1 kHz
06744-006
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PHASE NOISE (dBc/Hz)
RMS JITTER (12kHz TO 20MHz): 1.09ps
RMS JITTER (50kHz TO 80MHz): 1.14ps
Figure 6. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 Signal Generator at
50 MHz), f
REF
= 19.44 MHz, f
OUT
= 622.08 MHz, DPLL Loop BW = 1 kHz,
System Clock Doubler Enabled, HSTL Doubler Enabled
06744-007
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PHASE NOISE (dBc/Hz)
RMS JITTER (12kHz TO 20MHz): 1.0ps
RMS JITTER (50kHz TO 80MHz): 1.2ps
Figure 7. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 at 50 MHz), f
REF
= 19.44 MHz,
f
OUT
= 155.52 MHz, SYSCLK Doubler Enabled, DPLL Loop BW =1 kHz
06744-008
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PHASE NOISE (dBc/Hz)
RMS JITTER (12kHz TO 20MHz): 1.07ps
RMS JITTER (50kHz TO 80MHz): 1.16ps
Figure 8. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 Signal Generator at
50 MHz), f
REF
= 8 kHz, f
OUT
= 155.52 MHz, DPLL Loop BW = 10 Hz