Datasheet

Data Sheet AD9548
Rev. E | Page 99 of 112
Table 133. SYSCLK Status
Address Bits Bit Name Description
0x0D01 [7:5] Unused
[4] Stable The control logic sets this bit when the device considers the system clock to be
stable (see the System Clock Stability Timer section).
[3:2] Unused
[1] Cal in progress The control logic holds this bit set while the system clock calibration is in progress.
[0] Lock detected Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked (or the PLL is disabled).
Register 0x 0D02 to Register 0x0D09—IRQ Monitor
If not masked via the IRQ mask register (Address 0x0209 to Address 0x0210), then the appropriate IRQ monitor bit is set to a Logic 1
when the indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0x0A04 to Address 0x0A0B), the
reset all IRQs bit (Register 0x0A03, Bit 1), or a device reset.
Table 134. IRQ Monitor for SYSCLK
Address Bits Bit Name Description
0x0D02 [7:6] Unused
[5] SYSCLK unlocked Indicates a SYSCLK PLL state transition from locked to unlocked
[4] SYSCLK locked Indicates a SYSCLK PLL state transition from unlocked to locked
[3:2] Unused
[1] SYSCLK Cal complete Indicates that SYSCLK calibration has completed
[0] SYSCLK Cal started Indicates that SYSCLK calibration has begun
Table 135. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM
Address Bits Bit Name Description
0x0D03 [7:4] Unused
[3] Distribution sync Indicates a distribution sync event
[2] Watchdog timer Indicates expiration of the watchdog timer
[1] EEPROM fault Indicates a fault during an EEPROM load or save operation
[0] EEPROM complete Indicates successful completion of an EEPROM load or save operation
Table 136. IRQ Monitor for the Digital PLL
Address Bits Bit Name Description
0x0D04 [7] Switching Indicates that the DPLL is switching to a new reference
[6] Closed Indicates that the DPLL has entered closed-loop operation
[5] Freerun Indicates that the DPLL has entered free-run mode
[4]
Holdover
Indicates that the DPLL has entered holdover mode
[3] Freq unlocked Indicates that the DPLL lost frequency lock
[2] Freq locked Indicates that the DPLL has acquired frequency lock
[1]
Phase unlocked
Indicates that the DPLL lost phase lock
[0] Phase locked Indicates that the DPLL has acquired phase lock
Table 137. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit
Address
Bits
Bit Name
Description
0x0D05 [7:5] Unused
[4] History updated Indicates the occurrence of a tuning word history update
[3] Freq unclamped Indicates a frequency limiter state transition from clamped to unclamped
[2]
Freq clamped
Indicates a frequency limiter state transition from unclamped to clamped
[1] Phase slew unlimited Indicates a phase slew limiter state transition from slew limiting to not slew
limiting
[0] Phase slew limited Indicates a phase slew limiter state transition from not slew limiting to slew
limiting