Datasheet

AD9548 Data Sheet
Rev. E | Page 94 of 112
Table 120. Loop Mode
Address Bits Bit Name Description
0x0A01 [7] Unused
[6]
User holdover
Force the device into holdover mode.
0 (default) = normal operation.
1 = force device into holdover mode.
The device behaves as though all input references are faulted.
[5] User freerun Force the device into free-run mode.
0 (default) = normal operation.
1 = force device into free-run mode.
The free running frequency tuning word register specifies the DDS output frequency.
Note that, when the user freerun bit is set, it overrides the user holdover bit.
[4:3] User selection mode Select the operating mode of the reference switching state machine.
00 (default) = automatic mode. The fully automatic priority-based algorithm selects
the active reference (Bits[2:0] are ignored).
01 = fallback mode. The active reference is the user reference (Bits[2:0]) as long as it is
valid. Otherwise, use the fully automatic priority-based algorithm to select the active
reference.
10 = holdover mode. The active reference is the user reference (Bits[2:0]) as long as it
is valid. Otherwise, enter holdover mode.
11 = manual mode. The active reference is always the user reference (Bits[2:0]). When
using manual mode, be sure that the reference declared as the user reference
(Bits[2:0]) is programmed for manual reference-to-profile assignment in the
appropriate manual reference profile selection register (Address 0503 to Address
0506).
[2:0] User reference
selection
Input reference when user selection mode = 01, 10, or 11.
000 (default) = Input Reference A
001 = Input Reference AA
010 = Input Reference B
011 = Input Reference BB
100 = Input Reference C
101 = Input Reference CC
110 = Input Reference D
111 = Input Reference DD
Table 121. Cal/Sync
Address Bits Bit Name Description
0x0A02 [7:2] unused
[1] Sync distribution Setting this bit (default = 0) initiates synchronization of the clock distribution output.
While this bit = 1, the clock distribution output stalls. Synchronization occurs on the
1 to 0 transition of this bit.
[0] Calibrate system
clock
A 0 to 1 transition on this bit (default = 0), followed by an IO_UPDATE, initiates an
internal calibration of the SYSCLK PLL (assuming it is enabled). The calibration
routine automatically selects the proper VCO frequency band and signal amplitude.
The internal system clock stalls during the calibration procedure, disabling the
device until the calibration is complete (a few milliseconds). If the user wishes to
recalibrate the SYSCLK PLL and this bit is already set to 1, the user must first write a 0
to this bit, issue an IO_UPDATE, write a 1 to this bit, and issue another IO_UPDATE.