Datasheet

Data Sheet AD9548
Rev. E | Page 93 of 112
OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10)
Table 119. General Power-Down
Address Bits Bit Name Description
0x0A00
[7]
Reset sans reg map
Reset internal hardware but retain programmed register values.
0 (default) = normal operation.
1 = reset.
[6] Unused
[5] SYSCLK power-down Place SYSCLK input and PLL in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
[4] Reference power-
down
Place reference clock inputs in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
[3] TDC power-down Place the time-to-digital converter in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
[2] DAC power-down Place the DAC in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
[1] Dist power-down Place the clock distribution outputs in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
[0] Full power-down Place the entire device in deep sleep mode.
0 (default) = normal operation.
1 = power-down.