Datasheet

Data Sheet AD9548
Rev. E | Page 81 of 112
Table 74. Q3 Divider
1
Address Bits Bit Name Description
0x0414 [7:0] Q3 Q3 divider, Bits[7:0]
0x0415
[7:0]
Q3 divider, Bits[15:8]
0x0416 [7:0] Q3 divider, Bits[23:16]
0x0417 [7:6] Unused
[5:0] Q3 Q3 divider, Bits[29:24]
1
The default value is 0 (or divide by 1).
REFERENCE INPUT CONFIGURATION (REGISTER 0x0500 TO REGISTER 0x0507)
Table 75. Reference Power-Down
When all bits are set, the reference receiver section enters a deep sleep mode.
Address Bits Bit Name Description
0x0500 [7] Ref DD power-down REF DD input receiver power-down
0 (default) = normal operation
1 = power-down
[6]
Ref D power-down
REF D input receiver power-down
0 (default) = normal operation
1 = power-down
[5] Ref CC power-down REF CC input receiver power-down
0 (default) = normal operation
1 = power-down
[4] Ref C power-down REF C input receiver power-down
0 (default) = normal operation
1 = power-down
[3] Ref BB power-down REF BB input receiver power-down
0 (default) = normal operation
1 = power-down
[2] Ref B power-down REF B input receiver power-down
0 (default) = normal operation
1 = power-down
[1] Ref AA power-down REF AA input receiver power-down
0 (default) = normal operation
1 = power-down
[0] Ref A power-down REF A input receiver power-down
0 (default) = normal operation
1 = power-down