Datasheet

AD9548 Data Sheet
Rev. E | Page 80 of 112
Address Bits Bit Name Description
0x0407 [7:6] Unused
[5]
OUT3 CMOS phase
invert
When the output mode is CMOS, the bit inverts the relative phase between the two
CMOS output pins. Otherwise, this bit is nonfunctional.
0 (default) = not inverted.
1 = inverted.
[4] OUT3 polarity invert Invert the polarity of OUT3.
0 (default) = not inverted.
1 = inverted.
[3] OUT3 drive strength OUT3 output drive capability control.
0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.
1 = CMOS: normal drive strength; LVDS: 7 mA nominal.
[2:0] OUT3 mode OUT3 operating mode select.
000 = CMOS (both pins).
001 = CMOS (positive pin), tristate (negative pin).
010 = tristate (positive pin), CMOS (negative pin).
011 (default) = tristate (both pins).
100 = LVDS.
101 = LVPECL.
110 = reserved.
111 = reserved.
Register 0x0408 to Register 0x0417—Distribution Channel Dividers
Table 71. Q0 Divider
1
Address Bits Bit Name Description
0x0408 [7:0] Q0 Q0 divider, Bits[7:0]
0x0409 [7:0] Q0 divider, Bits[15:8]
0x040A [7:0] Q0 divider, Bits[23:16]
0x040B [7:6] Unused
[5:0] Q0 Q0 divider, Bits[29:24]
1
The default value is 0 (or divide by 1).
Table 72. Q1 Divider
1
Address Bits Bit Name Description
0x040C [7:0] Q1 Q1 divider, Bits[7:0]
0x040D [7:0] Q1 divider, Bits[15:8]
0x040E [7:0] Q1 divider, Bits[23:16]
0x040F
[7:6]
Unused
[5:0] Q1 Q1 divider, Bits[29:24]
1
The default value is 0 (or divide by 1).
Table 73. Q2 Divider
1
Address
Bits
Bit Name
Description
0x0410 [7:0] Q2 Q2 divider, Bits[7:0]
0x0411 [7:0] Q2 divider, Bits[15:8]
0x0412 [7:0] Q2 divider, Bits[23:16]
0x0413
[7:6]
Unused
[5:0] Q2 Q2 divider, Bits[29:24]
1
The default value is 0 (or divide by 1).