Datasheet

Data Sheet AD9548
Rev. E | Page 77 of 112
CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0419)
Table 66. Distribution Settings
1
Address Bits Bit Name Description
0x0400
[7:6]
Unused
[5] External distribution
resistor
Output current control for the clock distribution outputs
0 (default) = internal current setting resistor
1 = external current setting resistor
[4] Receiver mode Clock distribution receiver mode
0 (default) = normal operation
1 = high frequency mode (super-Nyquist)
[3] OUT3 power-down Power-down clock distribution output OUT3
0 (default) = normal operation
1 = power-down
[2] OUT2 power-down Power-down clock distribution output OUT2
0 (default) = normal operation
1 = power-down
[1] OUT1 power-down Power-down clock distribution output OUT1
0 (default) = normal operation
1 = power-down
[0] OUT0 power-down Power-down clock distribution output OUT0
0 (default) = normal operation
1 = power-down
1
When Bits[3:0] = 1111, the clock distribution output enters a deep sleep mode.
Table 67. Distribution Enable
Address Bits Bit Name Description
0x0401 [7:4] Unused
[3]
OUT3 enable
Enable the OUT3 driver.
0 (default) = disable.
1 = enable.
[2]
OUT2 enable
Enable the OUT2 driver.
0 (default) = disable.
1 = enable.
[1] OUT1 enable Enable the OUT1 driver.
0 (default) = disable.
1 = enable.
[0] OUT0 enable Enable the OUT0 driver.
0 (default) = disable.
1 = enable.