Datasheet

AD9548 Data Sheet

Rev. E | Page 76 of 112

Table 62. Incremental Closed-Loop Phase Lock Offset Step Size

Address Bits Bit Name Description

0x0314 [7:0] Incremental phase

lock offset step size

(expressed in pico-

seconds per step)

Incremental phase lock offset step size, Bits[7:0]

0x0315 [7:0] Incremental phase lock offset step size, Bits[15:8]

The default incremental closed-loop phase lock offset step size value is 0x03E8 = 1000 (1 ns).

Table 63. Phase Slew Rate Limit

Address Bits Bit Name Description

0x0316 [7:0] Phase slew limit

(expressed in nano-

seconds per second)

Phase slew rate limit, Bits[7:0]

0x0317 [7:0] Phase slew rate limit, Bits[15:8]

The default phase slew rate limit is 0 (or disabled).

Table 64. History Accumulation Timer

Address Bits Bit Name Description

0x0318 [7:0] History accumulation

timer (expressed in

milliseconds)

History accumulation timer, Bits[7:0]

0x0319 [7:0] History accumulation timer, Bits[15:8]

0x031A [7:0] History accumulation timer, Bits[23:16]

Do not program a timer value of 0. The history accumulation timer default value is 0x007530 = 30,000 (30 sec).

Table 65. History Mode

Address Bits Bit Name Description

0x031B [7:5] Unused

[4] Single-sample fallback Controls the holdover history. If tuning word history is not available for the

reference that was active just prior to holdover, then

0 (default) = use the free running frequency tuning word register value.

1 = use the last tuning word from the DPLL.

[3] Persistent history Controls the holdover history initialization. When switching to a new reference

0 (default) = clear the tuning word history.

1 = retain the previous tuning word history.

[2:0] Incremental average History mode value from 0 to 7 (default = 0).