Datasheet

Data Sheet AD9548
Rev. E | Page 71 of 112
SYSTEM CLOCK (REGISTER 0x0100 TO REGISTER 0x0108)
Table 43. Charge Pump and Lock Detect Control
Address Bits Bit Name Description
0x0100
[7]
External loop filter
enable
Enables use of an external SYSCLK PLL loop filter
0 (default) = internal loop filter
1 = external loop filter
[6] Charge pump mode Charge pump current control
0 (default) = automatic
1 = manual
[5:3] Charge pump current Selects charge pump current when Bit 6 = 1
000 = 125 μA
001 = 250 μA
010 = 375 μA
011 (default) = 500 μA
100 = 625 μA
101 = 750 μA
110 = 875 μA
111 = 1000 μA
[2] Lock detect timer
disable
Enable the SYSCLK PLL lock detect timer
0 (default) = enable
1 = disable
[1:0] Lock detect timer Select lock detect timer depth
00 (default) = 128
01 = 256
10 = 512
11 = 1024
Table 44. N Divider
Address Bits Bit Name Description
0x0101 [7:0] N-divider System clock PLL feedback divider value: 6 ≤ N ≤ 255 (default = 0x28 = 40)
Table 45. SYSCLK Input Options
Address Bits Bit Name Description
0x0102 [7] Unused
[6] M-divider reset Reset the M-divider
0 = normal operation
1 (default) = reset
When not using the M-divider, program this bit to Logic 1.
[5:4] M-divider System clock input divider
00 (default) = 1
01 = 2
10 = 4
11 = 8
[3] 2× frequency
multiplier enable
Enable the 2× frequency multiplier
0 (default) = disable
1 = enable
[2] PLL enable Enable the SYSCLK PLL
0 = disable
1 (default) = enable
[1:0] System clock source Input mode select for SYSCLKx pins
00 = crystal resonator
01 (default) = low frequency clock source
10 = high frequency (direct) clock source
11 = input receiver power-down