Datasheet

AD9548 Data Sheet
Rev. E | Page 18 of 112
TYPICAL PERFORMANCE CHARACTERISTICS
f
R
= input reference clock frequency; f
O
= clock frequency; f
SYS
= SYSCLK input frequency; f
S
= internal system clock frequency; LBW = DPLL
loop bandwidth; PLL off = SYSCLK PLL bypassed; PLL on = SYSCLK PLL enabled; I
CP
= SYSCLK PLL charge pump current; LF = SYSCLK
PLL loop filter. AVDD, AV DD3, and DVDD at nominal supply voltage, f
S
= 1 GHz, I
CP
= automatic mode, LF = internal, unless otherwise noted.
–160
–150
–140
–130
–120
–
1
10
–100
–90
–80
–70
100
1k
10k
100k
1M 10M
100M
PHASE NOISE (dBc/Hz)
FREQUENC
Y
OFFSET (Hz)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 173fs (–75.4dBc)
20kHz TO 80MHz: 315fs (–70.2dBc) (EXTRAPOLATED)
08022-068
Figure 3. Additive Phase Noise (Output Driver = LVPECL),
f
R
= 19.44 MHz, f
O
= 155.52 MHz,
LBW = 1 kHz, f
SYS
= 1 GHz, PLL Off
–160
–150
–140
–130
–120
–1
10
–100
–90
–80
–70
100
1k
10k
100k 1M
10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY
OFFSET (Hz)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 333fs (–69.8dBc)
20kHz TO 80MHz: 430fs (–67.6dBc) (EXTRAPOLATED)
08022-056
Figure 4. Additive Phase Noise (Output Driver = LVPECL),
f
R
= 19.44 MHz, f
O
= 155.52 MHz,
LBW = 1 kHz, f
SYS
= 50 MHz (Crystal), PLL On
–160
–150
–140
–130
–120
–
110
–100
–90
–80
–70
100
1k
10k
100k
1M
10M
100M
PHASE NOISE (dBc/Hz)
FREQUENC
Y OFFSET (Hz)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 103fs (–74.0dBc)
20kHz TO 80MHz: 160fs (–70.1dBc)
08022-066
Figure 5. Additive Phase Noise (Output Driver = LVPECL),
f
R
= 19.44 MHz, f
O
= 311.04 MHz,
LBW = 1 kHz, f
SYS
= 1 GHz, PLL Off
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
100
1k
10k
100k 1M
10M
100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 310fs (–64.4dBc)
20kHz TO 80MHz: 330fs (–63.9dBc)
08022-067
Figure 6. Additive Phase Noise (Output Driver = LVPECL),
f
R
= 19.44 MHz, f
O
= 311.04 MHz,
LBW = 1 kHz, f
SYS
= 50 MHz (Crystal), PLL On