Datasheet

Data Sheet AD9548
Rev. E | Page 15 of 112
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVDD
SCLK/SCL
SDIO
SDO
DVDD
DVDD3
TCLK
TMS
TDO
TDI
DVDD
RESET
DVDD
DVDD
NC
17VSS
18
DACOUTP
19
DACOUTN
20VSS
23 24
25 26
27
28 29
30 31
32
33 34
36 37
35 38
39 40 41
58
57
56
55
54
53
52
51
50
49
48
47
46
45
59
60
61
62
63
64
65
66
78
77 76
75 74
73
72 71
70 69
68
67 79
80
81 82
83 84
85
86
87
88
AD9548
TOP VIEW
(Not to Scale)
21
AVDD3
22
AVDD3
42 43 44
NC
AVDD
TDC_VRT
TDC_VRB
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).
REFB
REFBB
SYSCLK_VREG
AVDD3
AVDD
AVDD
SYSCLKN
SYSCLKP
VSS
VSS
REFA
REFAA
AVDD
AVDD3
M7
M6
M5
M4
DVDD
DVDD3
AVDD
AVDD
DVDD
IRQ
NC
AVDD3
REFDD
REFCC REFC
REFD
M3
M2
M1
M0
AVDD3
SYSCLK_LF
NC
NC
88-LEAD LFCSP
12mm × 12mm
0.5mm PITCH
AVDD3
DVDD
AVDD
VSS
CLKINN
CLKINP
VSS
AVDD
AVDD3
AVDD
AVDD
OUT1P
OUT1N
AVDD3
OUT2P
OUT3P
OUT3N
OUT2N
OUT_RSET
AVDD3
OUT0P
OUT0N
AVDD3
AVDD
08022-002
CS/SDA
Figure 2. 88-Lead LFCSP Pin Configuration
Table 21. Pin Function Descriptions
Pin No. Mnemonic
Input/
Output Pin Type Description
1, 6, 12, 77,
83, 88
DVDD I Power 1.8 V Digital Supply.
2
SCLK/SCL
I
3.3 V CMOS
Serial Programming Clock. Data clock for serial programming.
3 SDIO I/O 3.3 V CMOS Serial Data Input/Output. When the device is in 4-wire mode, data is written via
this pin. In 3-wire mode, both data reads and writes occur on this pin. There is no
internal pull-up/pull-down resistor on this pin.
4 SDO O 3.3 V CMOS Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in
3-wire mode). There is no internal pull-up/pull-down resistor on this pin.
5
CS
/SDA I 3.3 V CMOS Chip Select (SPI). Active low. When programming a device, this pin must be held
low. In systems where more than one AD9548 is present, this pin enables
individual programming of each AD9548 (in I
2
C® mode, this is a serial data pin).
This pin has an internal 10 kΩ pull-up resistor but only in SPI mode.
7, 82 DVDD3 I Power 3.3 V I/O Digital Supply.
8 TCLK I JTAG Clock. Internal pull-down resistor; no connection if JTAG is not used.
9
TMS
I
JTAG Mode. Internal pull-up resistor; no connection if JTAG is not used.
10 TDO O JTAG Output. No connection if JTAG is not used
11 TDI I JTAG Input. Internal pull-up resistor; no connection if JTAG is not used.
13 RESET I 3.3 V CMOS Chip Reset. When this active high pin is asserted, the chip goes into reset.
This pin has an internal 50 kΩ pull-down resistor.
14, 15 DVDD I Power 1.8 V DAC Decode Digital Supply. Keep isolated from the 1.8 V core digital supply.
16, 45, 46 NC No Connect.
17, 20, 25,
28, 51, 54
VSS O Ground Analog Ground. Connect to ground.
18 DACOUTP O Differential
output
DAC Output. DACOUTP contains an internal 50 Ω pull-down resistor.
19 DACOUTN O Differential
output
Complementary DAC Output. DACOUTN contains an internal 50 Ω pull-down
resistor.