Datasheet

Data Sheet AD9548
Rev. E | Page 13 of 112
Parameter Min Typ Max Unit Test Conditions/Comments
f
REF
= 19.44 Hz
1
; f
DDS
= 311.04 MHz
2
; f
LOOP
= 1 kHz
3
f
SYSCLK
= 50 MHz
4
crystal;
f
S
= 1 GHz
5
; Q-divider = 1; default SYSCLK
PLL charge pump current; results valid for
LVPECL, LVDS, and CMOS output logic types
Bandwidth: 100 Hz to 100 MHz
0.67
ps rms
Random jitter
Bandwidth: 5 kHz to 20 MHz 0.31 ps rms Random jitter
Bandwidth: 20 kHz to 80 MHz 0.33 ps rms Random jitter
Bandwidth: 50 kHz to 80 MHz 0.33 ps rms Random jitter
Bandwidth: 4 MHz to 80 MHz 0.16 ps rms Random jitter
1
f
REF
is the frequency of the active reference.
2
f
DDS
is the output frequency of the DDS.
3
f
LOOP
is the DPLL digital loop filter bandwidth.
4
f
SYSCLK
is the frequency at the SYSCLKP and SYSCLKN pins.
5
f
S
is the sample rate of the output DAC.