Datasheet

Data Sheet AD9548
Rev. E | Page 11 of 112
SERIAL PORT SPECIFICATIONS—SPI MODE
Table 17.
Parameter Min Typ Max Unit Test Conditions/Comments
CS
Internal 30 kΩ pull-up resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 30 µA
Input Logic 0 Current 110 µA
Input Capacitance 2 pF
SCLK Internal 30 kΩ pull-down resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 1 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
SDIO
As an Input
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 1 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
As an Output
Output Logic 1 Voltage 2.7 V 1 mA load current
Output Logic 0 Voltage 0.4 V 1 mA load current
SDO
Output Logic 1 Voltage 2.7 V 1 mA load current
Output Logic 0 Voltage 0.4 V 1 mA load current
TIMING
SCLK
Clock Rate, 1/t
CLK
40
MHz
Pulse Width High, t
HI
10 ns
Pulse Width Low, t
LO
12 ns
SDIO to SCLK Setup, t
DS
3 ns
SCLK to SDIO Hold, t
DH
0 ns
SCLK to Valid SDIO and SDO, t
DV
15 ns
CS
to SCLK Setup (t
S
) 10 ns
CS
to SCLK Hold (t
C
) 0 ns
CS
Minimum Pulse Width High 6 ns
SERIAL PORT SPECIFICATIONS—I
2
C MODE
Table 18.
Parameter Min Typ Max Unit Test Conditions/Comments
SDA, SCL (AS INPUT) No internal pull-up/down resistor.
Input Logic 1 Voltage 0.7 × DVDD3 V
Input Logic 0 Voltage 0.3 × DVDD3 V
Input Current −10 +10 µA For V
IN
= 10% to 90% DVDD3
Hysteresis of Schmitt Trigger Inputs 0.015 × DVDD3
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, t
SP
50 ns
SDA (AS OUTPUT)
Output Logic 0 Voltage
0.4
V
I
O
= 3 mA.
Output Fall Time from V
IHmin
to V
ILmax
20 + 0.1 C
b
1
250 ns 10 pF ≤ C
b
≤ 400 pF.