Datasheet

Data Sheet AD9548
Rev. E | Page 101 of 112
0x0D0B [7] Frequency clamped The upper or lower frequency tuning word clamp is in effect.
[6] History available There is sufficient tuning word history available for holdover operation.
[5:3] Active reference
priority
Priority value of the currently active reference.
000 = highest priority.
111 = lowest priority.
[2:0] Active reference Index of the currently active reference.
000 = Reference A.
001 = Reference AA.
010 = Reference B.
011 = Reference BB.
100 = Reference C.
101 = Reference CC.
110 = Reference D.
111 = Reference DD.
Table 140. Input Reference Status
Address Bits Bit Name Description
0x0D0C [7] Profile selected The control logic sets this bit when it assigns Ref A to one of the eight profiles.
[6:4] Selected profile The index (0 to 7) of the profile assigned to Ref A.
Note that these bits are meaningless unless Bit 7 = 1.
[3]
Valid
Ref A is valid for use (it is unfaulted and its validation timer has expired).
[2] Fault Ref A is not valid for use.
[1] Fast If Bit 7 = 1, then this bit indicates that the frequency of Ref A is higher than allowed
by its profile settings.
If Bit 7 = 0, then this bit indicates that the frequency of Ref A is above the maximum
input reference frequency supported by the device.
[0] Slow If Bit 7 = 1, then this bit indicates that the frequency of Ref A is lower than allowed by
its profile settings.
If Bit 7 = 0, then this bit indicates that the frequency of Ref A is below the minimum
input reference frequency supported by the device.
0x0D0D [7:0] Same as 0D0C but for REF AA instead of REF A.
0x0D0E [7:0] Same as 0D0C but for REF B instead of REF A.
0x 0D0F [7:0] Same as 0D0C but for REF BB instead of REF A.
0x0D10 [7:0] Same as 0D0C but for REF C instead of REF A.
0x0D11 [7:0] Same as 0D0C but for REF CC instead of REF A.
0x0D12 [7:0] Same as 0D0C but for REF D instead of REF A.
0x0D13 [7:0] Same as 0D0C but for REF DD instead of REF A.
Table 141. Holdover History
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Address Bits Bit Name Description
0x0D14 [7:0] Holdover history Tuning word readback, Bits[7:0]
0x0D15 [7:0] Tuning word readback, Bits[15:8]
0x0D16 [7:0] Tuning word readback, Bits[23:9]
0x0D17 [7:0] Tuning word readback, Bits[31:24]
0x0D18 [7:0] Tuning word readback, Bits[39:32]
0x0D19 [7:0] Tuning word readback, Bits[47:40]
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These registers contain the current 48-bit DDS frequency tuning word generated by the tuning word history logic.