Datasheet

ManualsBrandsANALOG DEVICES ManualsClock & Timing ICsAD9548BCPZ

Quad/Octal Input Network Clock

Generator/Synchronizer

Data Sheet

AD9548

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Supports Stratum 2 stability in holdover mode

Supports reference switchover with phase build-out

Supports hitless reference switchover

Auto/manual holdover and reference switchover

4 pairs of reference input pins with each pair configurable as

a single differential input or as 2 independent single-

ended inputs

Input reference frequencies from 1 Hz to 750 MHz

Reference validation and frequency monitoring (1 ppm)

Programmable input reference switchover priority

30-bit programmable input reference divider

4 pairs of clock output pins with each pair configurable as a

single differential LVDS/LVPECL output or as 2 single-

ended CMOS outputs

Output frequencies up to 450 MHz

30-bit integer and 10-bit fractional programmable feedback

divider

Programmable digital loop filter covering loop bandwidths

from 0.001 Hz to 100 kHz

Optional low noise LC-VCO system clock multiplier

Optional crystal resonator for system clock input

On-chip EEPROM to store multiple power-up profiles

Software controlled power-down

88-lead LFCSP package

APPLICATIONS

Network synchronization

Cleanup of reference clock jitter

GPS 1 pulse per second synchronization

SONET/SDH clocks up to OC-192, including FEC

Stratum 2 holdover, jitter cleanup, and phase transient

control

Stratum 3E and Stratum 3 reference clocks

Wireless base station controllers

Cable infrastructure

Data communications

GENERAL DESCRIPTION

The AD9548 provides synchronization for many systems,

including synchronous optical networks (SONET/SDH). The

AD9548 generates an output clock synchronized to one of up to

four differential or eight single-ended external input references.

The digital PLL allows for reduction of input time jitter or phase

noise associated with the external references. The AD9548

continuously generates a clean (low jitter), valid output clock

even when all references have failed by means of a digitally

controlled loop and holdover circuitry.

The AD9548 operates over an industrial temperature range of

−40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

REFERENCE INPUTS

AND

MONITOR MUX

STATUS AND

CONTROL PINS

SERIAL CONTROL INTERFACE

(SPI or I

EEPROM

DIGITAL

PLL

CLOCK DISTRIBUTION

SYNC

DAC

CLOCK

MULTIPLIER

STABLE

SOURCE

ANALOG

FILTER

AD9548

CHANNEL 0

DIVIDER

CHANNEL 1

DIVIDER

CHANNEL 2

DIVIDER

CHANNEL 3

DIVIDER

08022-001

Figure 1.

Summary of content (112 pages)

PAGE 1
Quad/Octal Input Network Clock Generator/Synchronizer AD9548 Data Sheet FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Auto/manual holdover and reference switchover 4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent singleended inputs Input reference frequencies from 1 Hz to 750 MHz Reference validation and frequency monitoring (1 ppm) P
PAGE 2
AD9548 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital PLL (DPLL) Core .......................................................... 32 Applications ....................................................................................... 1 Direct Digital Synthesizer ......................................................... 34 General Description ...................................................................
PAGE 3
Data Sheet AD9548 EEPROM Storage Sequence (Register 0x0E10 to Register 0x0E3F)...................................................................................... 102 Calculation of the  Register Values ......................................110 Power Supply Partitions .............................................................. 107 Calculation of the  Register Values .......................................111 3.3 V Supplies ........................................................................
PAGE 4
AD9548 Data Sheet SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1.8 V; TA= 25°C; IDAC = 20 mA (full scale), unless otherwise noted. SUPPLY VOLTAGE Table 1. Parameter SUPPLY VOLTAGE DVDD3 DVDD AVDD3 3.3 V Supply (Typical) 1.8 V Supply (Alternative) AVDD Min Typ Max Unit Test Conditions/Comments 3.135 1.71 3.135 3.135 1.71 1.71 3.30 1.80 3.
PAGE 5
Data Sheet Parameter Incremental Power Dissipation AD9548 Min Typ SYSCLK PLL Off Input Reference On Differential Single-Ended Output Distribution Driver On LVDS LVPECL CMOS Max Unit −105 mW 7 13 mW mW 70 75 65 mW mW mW Test Conditions/Comments Conditions = typical configuration; table values show the change in power due to the indicated operation. fSYSCLK = 1 GHz1; high frequency direct input mode. A single 3.3 V CMOS output with a 10 pF load.
PAGE 6
AD9548 Parameter SYSTEM CLOCK PLL ENABLED PLL Output Frequency Range Phase-Frequency Detector (PFD) Rate Frequency Multiplication Range VCO Gain High Frequency Path Input Frequency Range Minimum Input Slew Rate Frequency Divider Range Common-Mode Voltage Differential Input Voltage Sensitivity Input Capacitance Input Resistance Low Frequency Path Input Frequency Range Minimum Input Slew Rate Common-Mode Voltage Differential Input Voltage Sensitivity Input Capacitance Input Resistance Crystal Resonator Path
PAGE 7
Data Sheet AD9548 REFERENCE INPUTS (REFA/REFAA TO REFD/REFDD) Table 8.
PAGE 8
AD9548 Data Sheet REFERENCE SWITCHOVER SPECIFICATIONS Table 10.
PAGE 9
Data Sheet Parameter Rise/Fall Time1 (20% to 80%) 3.3 V Supply Strong Drive Strength Setting Weak Drive Strength Setting 1.8 V Supply Duty Cycle Output Voltage High (VOH) AVDD3 = 3.3 V, IOH = 10 mA AVDD3 = 3.3 V, IOH = 1 mA AVDD3 = 1.8 V, IOH = 1 mA Output Voltage Low (VOL) AD9548 Min Max Unit 0.5 8 1.5 2 14.5 2.5 60 ns ns ns % 40 2.6 2.9 1.5 AVDD3 = 3.3 V, IOL = 10 mA AVDD3 = 3.3 V, IOL = 1 mA AVDD3 = 1.8 V, IOL = 1 mA OUTPUT TIMING SKEW Between LVPECL Outputs Between LVDS Outputs Between CMOS 3.
PAGE 10
AD9548 Data Sheet TIME DURATION OF DIGITAL FUNCTIONS Table 13. Parameter TIME DURATION OF DIGITAL FUNCTIONS EEPROM-to-Register Download Time Min Typ Max Unit Test Conditions/Comments 25 ms Register-to-EEPROM Upload Time 200 ms Minimum Power-Down Exit Time Maximum Time from Assertion of the RESET pin to the M0 to M7 Pins Entering High Impedance State 10.
PAGE 11
Data Sheet AD9548 SERIAL PORT SPECIFICATIONS—SPI MODE Table 17.
PAGE 12
AD9548 Parameter TIMING SCL Clock Rate Bus-Free Time Between a Stop and Start Condition, tBUF Repeated Start Condition Setup Time, tSU; STA Repeated Hold Time Start Condition, tHD; STA Stop Condition Setup Time, tSU; STO Low Period of the SCL Clock, tLO High Period of the SCL Clock, tHI SCL/SDA Rise Time, tR SCL/SDA Fall Time, tF Data Setup Time, tSU; DAT Data Hold Time, tHD; DAT Capacitive Load for Each Bus Line, Cb1 1 Data Sheet Min Typ Max Unit 400 1.3 kHz µs 0.6 µs 0.6 µs 0.6 1.3 0.6 20 + 0.
PAGE 13
Data Sheet Parameter fREF = 19.44 Hz1; fDDS = 311.04 MHz2; fLOOP = 1 kHz3 Bandwidth: 100 Hz to 100 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz AD9548 Min Typ Max 0.67 0.31 0.33 0.33 0.16 fREF is the frequency of the active reference. fDDS is the output frequency of the DDS. 3 fLOOP is the DPLL digital loop filter bandwidth. 4 fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins. 5 fS is the sample rate of the output DAC.
PAGE 14
AD9548 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 20. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD3) DAC Supply Voltage (AVDD3) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 2V 2V 3.6 V 3.6 V −0.5 V to DVDD3 + 0.
PAGE 15
Data Sheet AD9548 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 DVDD M7 M6 M5 M4 DVDD DVDD3 M3 M2 M1 M0 DVDD IRQ NC AVDD AVDD3 REFDD REFD AVDD REFCC REFC AVDD3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AD9548 TOP VIEW (Not to Scale) 88-LEAD LFCSP 12mm × 12mm 0.
PAGE 16
AD9548 Data Sheet Pin No.
PAGE 17
Data Sheet AD9548 Input/ Output I Pin No. 53 Mnemonic SYSCLKP 56, 75 59 57, 58 NC AVDD TDC_VRB, TDC_VRT AVDD3 I I I Power I Power 3.3 V Analog (Reference Input) Power Supply. REFA I Differential input 62 REFAA I 63, 70, 74 64 AVDD REFB I I Differential input Power Differential input 65 REFBB I 68 REFC I 69 REFCC I 71 REFD I 72 REFDD I 76 78, 79, 80, 81, 84, 85, 86, 87 EP IRQ M0, M1, M2, M3, M4, M5, M6, M7 VSS O I/O Reference A Input.
PAGE 18
AD9548 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS fR = input reference clock frequency; fO = clock frequency; fSYS = SYSCLK input frequency; fS = internal system clock frequency; LBW = DPLL loop bandwidth; PLL off = SYSCLK PLL bypassed; PLL on = SYSCLK PLL enabled; ICP = SYSCLK PLL charge pump current; LF = SYSCLK PLL loop filter. AVDD, AVDD3, and DVDD at nominal supply voltage, fS = 1 GHz, ICP = automatic mode, LF = internal, unless otherwise noted.
PAGE 19
Data Sheet –70 AD9548 –70 INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 361fs (–69.0dBc) 20kHz TO 80MHz: 441fs (–67.3dBc) (EXTRAPOLATED) –80 –80 50MHz CRYSTAL –100 –110 –120 –130 –130 –150 –150 –160 100 –160 100 10k 100k 1M 10M 100M Figure 7. Additive Phase Noise (Output Driver = LVPECL), fR = 19.44 MHz, fO = 155.52 MHz, LBW = 1 kHz, fSYS = 50 MHz, PLL On 1k 10k 100k 1M 10M 100M Figure 10. Additive Phase Noise Comparison of SYSCLK Input Options (Output Driver = LVPECL), fR = 19.
PAGE 20
AD9548 Data Sheet –90 10 –100 0 –110 –10 CLOSED-LOOP GAIN (dB) –120 –130 ROHDE & SCHWARZ SMA100 (1GHz) –140 20MHz OCXO –150 –160 –20 –30 –40 –50 –60 ROHDE & SCHWARZ SMA100 (50MHz) 1k 10k 100k 1M 10M FREQUENCY OFFSET (Hz) –70 10 08022-053 –170 100 1k 100 Figure 16. Jitter Transfer Bandwidth, Output Driver = LVPECL, fR = 19.44 MHz, fO = 155.52 MHz, LBW = 100 Hz (Phase Margin = 88°), fSYS = 1 GHz, PLL Off Figure 13. Phase Noise of SYSCLK Input Sources 2.0 1.0 5pF LOAD 0.
PAGE 21
Data Sheet AD9548 40 140 130 20pF LOAD 35 120 LVPECL 10pF LOAD POWER (mW) POWER (mW) 110 100 90 80 5pF LOAD 30 25 LVDS 70 20 100 0 200 500 400 300 FREQUENCY (MHz) 15 08022-064 50 0 Figure 22. Power Consumption vs. Frequency, 1.
PAGE 22
AD9548 Data Sheet 3.5 3.5 10pF LOAD 5pF LOAD 3.0 3.0 20pF LOAD 2.5 1.5 1.0 1.0 0.5 0 0 0 2 4 6 8 10 12 14 16 TIME (ns) 2.0 10pF LOAD 1.5 20pF LOAD 1.0 0.5 –0.5 4 6 8 10 TIME (ns) 12 14 16 08022-065 0 2 –0.5 0 10 20 30 40 50 60 TIME (ns) Figure 27. Output Waveform, 3.3 V CMOS (20 MHz, Weak Mode) Figure 25. Output Waveform, 3.3 V CMOS (100 MHz, Strong Mode) 0 20 pF LOAD 1.5 0.5 –0.5 AMPLITUDE (V) 2.0 Figure 26. Output Waveform, 1.8 V CMOS (100 MHz) Rev.
PAGE 23
Data Sheet AD9548 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1µF 100Ω 100Ω HIGH IMPEDANCE INPUT (OPTIONAL) AD9548 3.3V LVDS OUTPUT 0.1µF DOWNSTREAM DEVICE 0.1µF 08022-006 08022-003 0.1µF AD9548 SELF-BIASED SYSCLK INPUT Figure 28. AC-Coupled LVDS or LVPECL Output Driver Figure 31. SYSCLKx Input AD9548 100Ω DOWNSTREAM DEVICE 100Ω 3.3V LVPECLCOMPATIBLE OUTPUT AD9548 SELF-BIASED CLKINx INPUT 08022-007 08022-004 0.1µF (OPTIONAL) 0.1µF Figure 29.
PAGE 24
AD9548 Data Sheet GETTING STARTED POWER-ON RESET The AD9548 monitors the voltage on the power supplies at power-up. When DVDD3 is greater than 2.35 V ± 0.1 V and DVDD (Pin 1, Pin 6, Pin 12, Pin 77, Pin 83, and Pin 88) is greater than 1.4 V ± 0.05 V, the device generates a 75 ns reset pulse. The power-up reset pulse is internal and independent of the RESET pin. This internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing.
PAGE 25
Data Sheet AD9548 Program the Clock Distribution Outputs Generate the Reference Acquisition The clock distribution parameters reside in the 0x0400 register address space. They include the following: After the registers are programmed, issue an I/O update using Register 0x0005, Bit 0 to invoke all of the register settings programmed up to this point.
PAGE 26
AD9548 Data Sheet THEORY OF OPERATION OUT_RSET AD9548 REFA REFAA DIFFERENTIAL OR SINGLE-ENDED REFB REFBB REFC REFCC DIGITAL PLL CORE ÷S REFD REFDD TDC/PFD ÷R PROG.
PAGE 27
Data Sheet AD9548 REFERENCE CLOCK INPUTS Four pairs of pins provide access to the reference clock receivers. Each pair is configurable either as a single differential receiver or as two independent single-ended receivers. To accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. Hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate spontaneously.
PAGE 28
AD9548 Data Sheet REGISTER CONTROL BITS REFERENCE VALIDATION LOGIC (8 COPIES, 1 PER REFERENCE INPUT) D Q VALID FORCE VALIDATION TIMEOUT VALIDATION TIMER REF MONITOR BYPASS REF MONITOR OVERRIDE R 1 EN R TIMEOUT FAULTED REFERENCE MONITOR 08022-010 0 REF FAULT Figure 35. Reference Validation Override The main feature to note is that any time faulted = 1, the output latch is reset, which forces valid = 0 (indicating an invalid reference) regardless of the state of any other signal.
PAGE 29
Data Sheet AD9548 The MSB of each nibble is the manual profile bit, whereas the three LSBs of each nibble identify one of the eight profiles (0 to 7). A Logic 1 for the manual profile bit assigns the associated reference to the profile identified by the three LSBs of the nibble. A Logic 0 for the manual profile bit configures the associated reference for automatic reference-to-profile assignment (the three LSBs are ignored in this case).
PAGE 30
AD9548 Data Sheet REFERENCE SWITCHOVER An attractive feature of the AD9548 is its versatile reference switchover capability. The flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm coupled with register-based controls. This scheme provides the user with maximum control over the state machine that handles reference switchover. The main reference switchover control resides in the loop mode (Address 0x0A01).
PAGE 31
Data Sheet AD9548 Priority 3 reference is active, its promoted priority of 1 is in effect. This is a higher priority than the newly validated reference’s priority of 2, so the switchover does not occur. This mechanism enables the user to give references preferential treatment while they are selected as the active reference. An example of promoted vs. nonpromoted priority switching appears in state diagram form in Figure 36.
PAGE 32
AD9548 Data Sheet Phase build-out reference switching is the term given to a reference switchover that completely masks any phase difference between the previous reference and the new reference. That is, there is virtually no phase change detectable at the output when a phase build-out switchover occurs. The AD9548 handles phase build-out switching based on whether the new reference is a phase master.
PAGE 33
Data Sheet AD9548 The DPLL includes a feedback divider that causes the DDS to operate at an integer-plus-fractional multiple (S + 1 + U/V) of fTDC. S is the 30-bit value stored in the profile register and has a range of 7 ≤ S ≤ 1,073,741,823. U and V are the 10-bit numerator and denominator values of the optional fractional divide component and are also stored in the profile register.
PAGE 34
AD9548 Data Sheet Each coefficient has a fractional component representing a value from 0 up to, but not including, unity. Each coefficient also has an exponential component representing a power of 2 with a negative exponent. That is, the user enters a positive number (x) that the hardware interprets as a negative exponent of two (2−x). Thus, the ,  and  coefficients always represent values less than unity.
PAGE 35
Data Sheet AD9548 48-BIT ACCUMULATOR PHASE OFFSET 48 48 19 48 D 19 14 ANGLE TO AMPLITUDE CONVERSION Q DAC+ DAC (14-BIT) DAC– 08022-018 FREQUENCY TUNING WORD (FTW) 16 fS Figure 43. DDS Block Diagram AVDD3 The input to the DDS is the 48-bit FTW. The FTW serves as a step size value. On each cycle of fS, the accumulator adds the value of the FTW to the running total at its output. For example, given FTW = 5, the accumulator counts by fives, incrementing on each fS cycle.
PAGE 36
AD9548 Data Sheet When the DPLL is in free-run mode, the DDS tuning word is the value stored in the free running frequency tuning word register (Address 0x0300 to Address 0x0305). When the DPLL is operating normally (closed loop), the DDS tuning word comes from the output of the digital loop filter, which changes dynamically in order to maintain phase lock with the input reference signal (assuming that the device has not performed an automatic switch to holdover mode).
PAGE 37
Data Sheet AD9548 Switchover Switchover occurs when the loop controller switches directly from one input reference to another. Functionally, the AD9548 handles a reference switchover by briefly entering holdover mode and then immediately recovering. During the switchover event, however, the AD9548 preserves the status of the lock detectors to avoid phantom unlock indications. Holdover The holdover state of the DPLL is an open-loop operating mode.
PAGE 38
AD9548 Data Sheet LF SYSCLKN 52 SYSCLK_VREG SYSCLK_LF 48 49 2× LOCK DETECT ÷M PFD AND CHARGE PUMP XTAL VCO CALIBRATION LOOP FILTER SYSCLKP 53 ÷N SYSTEM CLOCK 08022-020 HF Figure 46. System Clock Block Diagram System Clock Details A block diagram of the system clock appears in Figure 46. The signal at the SYSCLKx input pins becomes the internally buffered DAC sampling clock (fS) via one of three paths.
PAGE 39
Data Sheet AD9548 samples grows larger. Thus, one way of indicating a locked condition is to count the number of consecutive in-phase PFD samples and if it exceeds a certain value, then declare the PLL locked. This is exactly the role of the lock detect divider bits. When the lock detector is enabled (Register 0x0100, Bit 2 = 0), the lock detect divider bits determine the number of consecutive in-phase decisions required (128, 256, 512, or 1024) before the lock detector declares a locked condition.
PAGE 40
AD9548 Data Sheet Note that the monitors/detectors associated with the input references (REFA/AA – REFD/DD) are internally disabled until the SYSCLK PLL indicates that it is stable. CLOCK DISTRIBUTION The clock distribution block of the AD9548 provides an integrated solution for generating multiple clock outputs based on frequency dividing the DPLL output. The distribution output consists of four channels (OUT0 to OUT3).
PAGE 41
Data Sheet AD9548 of runt pulses and ensure that outputs with the same divide ratios become active/inactive in unison. Output Mode The user has independent control of the operating mode of each of the four output channels via the distribution channel modes register (Address 0x0404 to Address 0x0407).
PAGE 42
AD9548 Data Sheet then clears the bit. The synchronization event is the clearing operation; that is, the Logic 1 to Logic 0 transition of the bit. The primary synchronization signal can synchronize the distribution output directly or it can enable a secondary synchronization signal. This functionality depends on the two sync source bits in the distribution synchronization register (Register 0x0402, Bits[5:4]).
PAGE 43
Data Sheet DIRECT SYNC SOURCE (REGISTER 0A02[1]) AD9548 REGISTER 0402[5] PRIMARY SYNCHRONIZATION SIGNAL DIRECT SYNC AUTOMATIC SYNC SOURCE (REGISTER 0403) EEPROM SYNC SOURCE 0 TO CLOCK DISTRIBUTION SYNCHRONIZATION CONTROL 1 EDGE DETECT MULTIFUNCTION PIN SYNC SOURCE TO MULTIFUNCTION PIN STATUS LOGIC DPLL FEEDBACK EDGE ARM STALL DIVIDERS SYNC OUTPUT DISTRIBUTION EDGE DETECT SYSCLK/4 DPLL EDGE SYNC REGISTER 0402[4] RESET ARM REF A REF AA EDGE DETECT ACTIVE REFERENCE SYNC 08022-023 REF D RE
PAGE 44
AD9548 Data Sheet STATUS AND CONTROL MULTIFUNCTION PINS (M0 TO M7) The AD9548 has eight digital CMOS I/O pins (M0 to M7) that are configurable for a variety of uses. The function of these pins is programmable via the register map. Each pin can control or monitor an assortment of internal functions based on the contents of Register 0x0200 to Register 0x0207.
PAGE 45
Data Sheet AD9548 To control an internal function with a multifunction pin, write a Logic 0 to the most significant bit of the register associated with the desired multifunction pin. The monitored function depends on the value of the seven least significant bits of the register, as shown in Table 26. Table 26.
PAGE 46
AD9548 Data Sheet The watchdog timer is a general-purpose programmable timer. To set the timeout period, the user writes to the 16-bit watchdog timer register (Address 0x0211 to Address 0x0212). A value of 0 in this register disables the timer. A nonzero value sets the timeout period in milliseconds, giving the watchdog timer a range of 1 ms to 65.535 sec. The relative accuracy of the timer is approximately 0.1% with an uncertainty of 0.5 ms.
PAGE 47
Data Sheet AD9548 Table 27. EEPROM Controller Instruction Set Instruction Value (Hex) 0x00 to 0x7F Instruction Type Data Bytes Required 3 0x80 I/O update 1 0xA0 Calibrate 1 0xA1 Distribution sync 1 0xB0 to 0xCF Condition 1 0xFE Pause 1 0xFF End 1 Description A data instruction tells the controller to transfer data to or from the device settings part of the register map. A data instruction requires two additional bytes that together indicate a starting address in the register map.
PAGE 48
AD9548 Data Sheet A pause instruction, like an end instruction, is stored at the end of a sequence of instructions in the scratch pad. When the controller encounters a pause instruction during an upload sequence, it keeps the EEPROM address pointer at its last value. This way the user can store a new instruction sequence in the scratch pad and upload the new sequence to the EEPROM. The new sequence is stored in the EEPROM address locations immediately following the previously saved sequence.
PAGE 49
Data Sheet AD9548 CONDITION TAG BOARD EXAMPLE CONDITION 3 AND CONDITION 13 ARE TAGGED M7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IF B1 ≤ INSTRUCTION ≤ CF, THEN TAG DECODED CONDITION IF INSTRUCTION = B0, THEN CLEAR ALL TAGS EEPROM UPLOAD PROCEDURE 5 5 IF {0E01, BITS[4:0] ≠ 0} CONDITION = 0E01, BITS[4:0] ELSE CONDITION = FncInit, BITS[7:3] ENDIF 5 COND ITION CONDITION HANDLER SCRATCH PAD FncInit, BITS[7:3] EXECUTE/SKIP IN
PAGE 50
AD9548 Data Sheet Table 28 lists a sample EEPROM download instruction sequence. It illustrates the use of condition instructions and how they alter the download sequence. The table begins with the assumption that no conditions are in effect. That is, the most recently executed condition instruction is 0xB0 or no conditional instructions have been processed. 2. Table 28.
PAGE 51
Data Sheet AD9548 SERIAL CONTROL PORT SCLK/SCL CS/SDA SDIO SDO 13-BIT ADDRESS SPACE SPI READ ONLY REGION 2 IC EEPROM POWER-ON RESET EEPROM CONTROLLER MULTIFUNCTION PIN CONTROL LOGIC READ/WRITE REGION ANALOG BLOCKS AND DIGITAL CORE 400kHz M7 M6 M5 M4 M3 M2 M1 M0 08022-026 SERIAL CONTROL ARBITER Figure 52.
PAGE 52
AD9548 Data Sheet SPI Mode Operation Write The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration and data format features are programmable. By default, the AD9548 uses the bidirectional MSB-first mode. The reason that bidirectional is the default mode is so that the user can still write to the device, if it is wired for unidirectional operation, to switch to unidirectional mode.
PAGE 53
Data Sheet AD9548 SPI Instruction Word (16 Bits) includes the register address of the least significant payload byte followed by multiple data bytes. The serial control port internal byte address generator increments for each byte of the multibyte transfer cycle. The MSB of the 16-bit instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits, W1 and W0, indicate the number of bytes in the transfer (see Table 30).
PAGE 54
AD9548 Data Sheet tDS tHIGH tDH SCLK DON'T CARE SDIO DON'T CARE R/W W1 tC tCLK tLOW CS W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 HIGH-IMEPDANCE 08022-153 tS Figure 56. Serial Control Port Read—MSB First, 16-Bit Instruction, One Byte of Data tDS tHI tS CS DON'T CARE SDIO DON'T CARE tLO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 08022-031 SCLK tC tCLK tDH Figure 57.
PAGE 55
Data Sheet AD9548 Table 33. Serial Control Port Timing Parameter tDS tDH tCLK tS tC tHI tLO tDV Description Setup time between data and the rising edge of SCLK. Hold time between data and the rising edge of SCLK. Period of the clock. Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle). Setup time between the SCLK rising edge and the CS rising edge (end of the communication cycle).
PAGE 56
AD9548 Data Sheet I²C SERIAL PORT OPERATION I2C Bus Characteristics The I2C interface has the advantage of requiring only two control pins and is a de facto standard throughout the I2C industry. However, its disadvantage is programming speed, which is 400 kbps maximum. The AD9548 I2C port design is based on the I2C fast mode standard from Philips, so it supports both the 100 kHz standard mode and 400 kHz fast mode. Fast mode imposes a glitch tolerance requirement on the control signals.
PAGE 57
Data Sheet AD9548 The acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. It is done by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte.
PAGE 58
AD9548 Data Sheet Data Transfer Format Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. S Slave address A W RAM address high byte A RAM address low byte A RAM Data 0 A RAM Data 1 A RAM Data 2 A P Send byte format—the send byte protocol is used to set up the register address for subsequent reads.
PAGE 59
Data Sheet AD9548 Note that the EEPROM storage sequence registers (Address 0x0E10 to Address 0x0E3F) are an exception to the above convention (see the EEPROM Instructions section). BUFFERED/ACTIVE REGISTERS There are two broad categories of registers in the AD9548, buffered and active (see Figure 67). Buffered registers are those that can be written to directly from the serial port. They do not need an I/O update to apply their contents to the internal device functions.
PAGE 60
AD9548 Data Sheet REGISTER MAP The register addresses and defaults are hexadecimal values. Use the default value when writing to registers and/or bits marked as unused. Table 36.
PAGE 61
Data Sheet AD9548 Addr 0x0211 0x0212 0x0213 0x0214 Opt C C S S Name Watchdog timer D7 D6 D5 D4 D3 D2 Watchdog timer (ms) [15:0] [up to 65.
PAGE 62
AD9548 Data Sheet Addr Opt 0x0408 S 0x0409 S 0x040A S 0x040B S 0x040C S 0x040D S 0x040E S 0x040F S 0x0410 S 0x0411 S 0x0412 S 0x0413 S 0x0414 S 0x0415 S 0x0416 S 0x0417 S Reference Inputs 0x0500 S Name Distribution channel dividers 0x0501 0x0502 0x0503 S S C Reference logic family 0x0504 C 0x0505 C 0x0506 C 0x0507 C D6 D5 D4 D3 Q0 [23:0] Unused D2 D1 D0 Q0 [29:24] Q1 [23:0] Unused Q1 [29:24] Q2 [23:0] Unused Q2 [29:24] Q3 [23:0] Unused Reference power-down Manual reference profi
PAGE 63
Data Sheet Addr 0x0612 0x0613 Opt Name Digital loop filter coefficients 0x0614 0x0615 D7 D6 D5 D4 D3 Alpha-0 linear [15:0] Alpha-2 exponent [1:0] D2 D1 D0 Alpha-1 exponent [5:0] Beta-0 linear [6:0] 0x0616 0x0617 0x0618 0x0619 0x061A Unused Reference period Tolerance Beta-0 linear [16:15] Gamma-1 exponent [4:0] Gamma-0 linear [16] Delta-0 linear [7:0] Delta-0 linear [14:8] Delta-1 exponent [0] 0x061D 0x061E Frequency multiplica0x061F tion 0x0620 0x0621 0x0622 0x0623 0x0624 0x0625 0x062
PAGE 64
AD9548 Addr 0x0644 0x0645 0x0646 0x0647 Opt Data Sheet Name Digital loop filter coefficients D6 D5 D4 D3 Alpha-0 linear [15:0] Alpha-2 exponent [1:0] D2 D1 D0 Alpha-1 exponent [5:0] Beta-0 linear [6:0] 0x0648 0x0649 0x064A 0x064B 0x064C Unused Reference period Tolerance Beta-0 linear [16:15] Gamma-1 exponent [4:0] Gamma-0 linear [16] Delta-0 linear [7:0] Delta-0 linear [14:8] Delta-1 exponent [0] 0x064F 0x0650 Frequency multiplica0x0651 tion 0x0652 0x0653 0x0654 0x0655 0x0656 0x0657 0x0
PAGE 65
Data Sheet Addr 0x0692 0x0693 0x0694 0x0695 Opt Name Digital loop filter coefficients D7 D6 D5 D4 D3 Alpha-0 linear [15:0] Alpha-2 exponent [1:0] D2 D1 D0 Alpha-1 exponent [5:0] Beta-0 linear [6:0] 0x0696 0x0697 0x0698 0x0699 0x069A Unused Reference period Tolerance Beta-0 linear [16:15] Gamma-1 exponent [4:0] Gamma-0 linear [16] Delta-0 linear [7:0] Delta-0 linear [14:8] Delta-1 exponent [0] 0x069D 0x069E Frequency multiplica0x069F tion 0x06A0 0x06A1 0x06A2 0x06A3 0x06A4 0x06A5 0x06A6
PAGE 66
AD9548 Addr 0x06C4 0x06C5 0x06C6 0x06C7 0x06C8 0x06C9 0x06CA 0x06CB 0x06CC 0x06CD 0x06CE Opt Data Sheet Name Digital loop filter coefficients D7 D6 D5 D4 D3 Alpha-0 linear [15:0] Alpha-2 exponent [1:0] D2 D1 Alpha-1 exponent [5:0] Beta-0 linear [6:0] Beta-0 linear [14:7] Beta-1 exponent [4:0] Unused D0 Alpha-2 exponent [2] 0x00 Beta-0 linear [16:15] 00 Gamma-0 linear [15:0] Unused Delta-1 exponent [0] Gamma-1 exponent [4:0] Gamma-0 linear [16] Delta-0 linear [7:0] Delta-0 linear [14:8]
PAGE 67
Data Sheet Addr Opt 0x0A09 Name AD9548 D7 new profile D6 validated A, C Ref BB new profile Ref BB validated 0x0A0A A, C Ref CC new profile Ref CC validated 0x0A0B A, C Ref DD new profile Ref DD validated 0x0A0C A, C 0x0A0D A, C Incremental phase offset D5 fault cleared Ref BB fault cleared Ref CC fault cleared Ref DD fault cleared Unused D4 fault D3 new profile D2 validated Ref BB fault Ref B new profile Ref B validated Ref CC fault Ref C new profile Ref C validated Ref DD fa
PAGE 68
AD9548 Data Sheet Addr 0x0D0C Opt R, C Name Ref A 0x0D0D R, C Ref AA 0x0D0E R, C Ref B 0x0D0F R, C Ref BB 0x0D10 R, C Ref C 0x0D11 R, C Ref CC 0x0D12 R.
PAGE 69
Data Sheet Addr 0x0E2E 0x0E2F 0x0E30 0x0E31 0x0E32 0x0E33 0x0E34 to 0x0E3F Opt E E E E E E E Name I/O update Operational controls I/O update End of data AD9548 D7 D6 D5 D4 D3 Action: I/O update Data: 17 bytes Address: 0x0A00 Action: I/O update Action: end of data Continuation of scratch pad area Rev.
PAGE 70
AD9548 Data Sheet REGISTER MAP BIT DESCRIPTIONS SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005) Table 37. Serial Configuration Address 0x0000 Bits [7] Bit Name Unidirectional [6] LSB first [5] Soft reset [4] Long instruction [0] Unused Description Select SPI port SDO pin operating mode. 0 (default) = 3-wire. 1 = 4-wire (SDO pin enabled). Bit order for SPI port. 0 (default) = most significant bit and byte first. 1 = least significant bit and byte first.
PAGE 71
Data Sheet AD9548 SYSTEM CLOCK (REGISTER 0x0100 TO REGISTER 0x0108) Table 43.
PAGE 72
AD9548 Data Sheet Table 46. Nominal System Clock (SYSCLK) Period 1 Address 0x0103 Bits [7:0] 0x0104 [7:0] 0x0105 [7:5] [4:0] 1 Bit Name System clock period (expressed in femtoseconds) Unused System clock period Description System clock period, Bits[7:0] System clock period, Bits[15:8] System clock period, Bits[20:16] Units are femtoseconds. The default value is 0x0F424 = 1,000,000 (1 ns) and implies a system clock frequency of 1 GHz. Table 47.
PAGE 73
Data Sheet AD9548 Register 0x0209 to Register 0x0210—IRQ Mask The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0x0D02 to Address 0x0D09). When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts. Table 50.
PAGE 74
AD9548 Data Sheet Table 54.
PAGE 75
Data Sheet AD9548 DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x031B) Table 57.
PAGE 76
AD9548 Data Sheet Table 62. Incremental Closed-Loop Phase Lock Offset Step Size 1 Address 0x0314 Bits [7:0] 0x0315 [7:0] 1 Bit Name Incremental phase lock offset step size (expressed in picoseconds per step) Description Incremental phase lock offset step size, Bits[7:0] Incremental phase lock offset step size, Bits[15:8] The default incremental closed-loop phase lock offset step size value is 0x03E8 = 1000 (1 ns). Table 63.
PAGE 77
Data Sheet AD9548 CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0419) Table 66.
PAGE 78
AD9548 Data Sheet Table 68. Distribution Synchronization Address 0x0402 Bits [7:6] [5:4] Bit Name Unused Sync source [3] OUT3 sync mask [2] OUT2 sync mask [1] OUT1 sync mask [0] OUT0 sync mask Description Select the sync source for the clock distribution output channels. 00 (default) = direct. 01 = active reference. 10 = DPLL feedback edge. 11 = reserved. Mask the synchronous reset to the OUT3 divider. 0 (default) = unmasked 1 = masked. Mask the synchronous reset to the OUT2 divider.
PAGE 79
Data Sheet Address 0x0405 0x0406 AD9548 Bits [7:6] [5] Bit Name Unused OUT1 CMOS phase invert [4] OUT1 polarity invert [3] OUT1 drive strength [2:0] OUT1 mode [7:6] [5] Unused OUT2 CMOS phase invert [4] OUT2 polarity invert [3] OUT2 drive strength [2:0] OUT2 mode Description When the output mode is CMOS, the bit inverts the relative phase between the two CMOS output pins. Otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. Invert the polarity of OUT1.
PAGE 80
AD9548 Address 0x0407 Data Sheet Bits [7:6] [5] Bit Name Unused OUT3 CMOS phase invert [4] OUT3 polarity invert [3] OUT3 drive strength [2:0] OUT3 mode Description When the output mode is CMOS, the bit inverts the relative phase between the two CMOS output pins. Otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. Invert the polarity of OUT3. 0 (default) = not inverted. 1 = inverted. OUT3 output drive capability control. 0 (default) = CMOS: low drive strength; LVDS: 3.
PAGE 81
Data Sheet AD9548 Table 74. Q3 Divider 1 Address 0x0414 0x0415 0x0416 0x0417 1 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name Q3 Unused Q3 Description Q3 divider, Bits[7:0] Q3 divider, Bits[15:8] Q3 divider, Bits[23:16] Q3 divider, Bits[29:24] The default value is 0 (or divide by 1). REFERENCE INPUT CONFIGURATION (REGISTER 0x0500 TO REGISTER 0x0507) Table 75. Reference Power-Down When all bits are set, the reference receiver section enters a deep sleep mode.
PAGE 82
AD9548 Data Sheet Table 76. Reference Logic Family Address 0x0501 0x0502 Bits [7:6] Bit Name Ref BB logic family [5:4] Ref B logic family [3:2] [1:0] [7:6] [5:4] [3:2] [1:0] Ref AA logic family Ref A logic family Ref DD logic family Ref D logic family Ref CC logic family Ref C logic family Description Select the logic family for the REF BB input receiver (ignored if Bits[5:4] = 00) 00 (default) = disabled 01 = 1.2 V to 1.5 V CMOS 10 = 1.8 V to 2.5 V CMOS 11 = 3.0 V to 3.
PAGE 83
Data Sheet AD9548 Table 78. Phase Build-Out Switching Address 0x0507 Bits [7:3] [2:0] Bit Name Unused Phase master threshold priority Description Threshold priority level (a value of 0 to 7, with 0 (default) being the highest priority level). References with a selection priority value lower than this value are treated as phase masters (see the Profile Registers (Register 0x0600 to Register 0X07FF) section for the selection priority value).
PAGE 84
AD9548 Data Sheet Table 84.
PAGE 85
Data Sheet AD9548 Table 87. Fractional Feedback Divider—Profile 0 Address 0x0626 0x0627 0x0628 Bits [7:0] [7:4] [3:2] [1:0] [7:6] [5:0] Bit Name V U Unused V Unused U Description V, Bits[7:0] U, Bits[3:0] V, Bits[9:8] U, Bits[9:4] Table 88.
PAGE 86
AD9548 Data Sheet Table 91. Tolerance—Profile 1 Address 0x063A 0x063B 0x063C 0x063D 0x063E 0x063F Bits [7:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:4] [3:0] Bit Name Inner tolerance Unused Inner tolerance Outer tolerance Unused Outer tolerance Description Inner tolerance, Bits[7:0] Inner tolerance, Bits[15:8] Inner tolerance, Bits[19:16] Outer tolerance, Bits[7:0] Outer tolerance, Bits[15:8] Outer tolerance, Bits[19:16] Table 92.
PAGE 87
Data Sheet AD9548 Table 95. R-Divider—Profile 1 1 Address 0x0650 0x0651 0x0652 0x0653 1 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name R Unused R Description R, Bits[7:0] R, Bits[15:8] R, Bits[23:16] R, Bits[29:24] The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value. Table 96.
PAGE 88
AD9548 Data Sheet Register 0x0680 to Register 0x06B1—Profile 2 Table 99. Priorities—Profile 2 Address 0x0680 Bits [7] Bit Name Phase lock scale [6] [5:3] Unused Promoted priority [2:0] Selection priority Description Controls the phase lock threshold unit scaling. 0 = picoseconds. 1 = nanoseconds. User assigned priority level (0 to 7) of the reference associated with Profile 2 while that reference is the active reference.
PAGE 89
Data Sheet AD9548 Table 104.
PAGE 90
AD9548 Data Sheet Table 108.
PAGE 91
Data Sheet AD9548 Table 113. Redetect Timer—Profile 3 Address 0x06C2 0x06C3 Bits [7:0] [7:0] Bit Name Redetect timer (in milliseconds) Description Redetect timer, Bits[7:0] Redetect timer, Bits[15:8] Table 114.
PAGE 92
AD9548 Data Sheet Table 117. Fractional Feedback Divider—Profile 3 Address 0x06D8 0x06D9 0x06DA Bits [7:0] [7:4] [3:2] [1:0] [7:6] [5:0] Bit Name V U Unused V Unused U Description V, Bits[7:0] U, Bits[3:0] V, Bits[9:8] U, Bits[9:4] Table 118.
PAGE 93
Data Sheet AD9548 OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10) Table 119. General Power-Down Address 0x0A00 Bits [7] Bit Name Reset sans reg map [6] [5] Unused SYSCLK power-down [4] Reference powerdown [3] TDC power-down [2] DAC power-down [1] Dist power-down [0] Full power-down Description Reset internal hardware but retain programmed register values. 0 (default) = normal operation. 1 = reset. Place SYSCLK input and PLL in deep sleep mode. 0 (default) = normal operation.
PAGE 94
AD9548 Data Sheet Table 120. Loop Mode Address 0x0A01 Bits [7] [6] Bit Name Unused User holdover [5] User freerun [4:3] User selection mode [2:0] User reference selection Description Force the device into holdover mode. 0 (default) = normal operation. 1 = force device into holdover mode. The device behaves as though all input references are faulted. Force the device into free-run mode. 0 (default) = normal operation. 1 = force device into free-run mode.
PAGE 95
Data Sheet AD9548 Register 0x0A03—ResetFunc Table 122. Reset Functions 1 Address 0x0A03 1 Bits [7] [6] [5] [4] [3] Bit Name Unused Clear LF Clear CCI Clear phase accumulator Reset auto sync [2] Reset TW history [1] Reset all IRQs [0] Reset watchdog Description Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool). Setting this bit (default = 0) clears the CCI filter (intended as a debug tool).
PAGE 96
AD9548 Data Sheet Table 126. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit Address 0x0A07 Bits [7:5] [4] [3] [2] [1] [0] Bit Name Unused History updated Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Description Clears history updated IRQ Clears frequency unclamped IRQ Clears frequency clamped IRQ Clears phase slew unlimited IRQ Clears phase slew limited IRQ Table 127.
PAGE 97
Data Sheet AD9548 Table 128. Incremental Phase Offset Control Address 0x0A0C Bits [7:3] [2] Bit Name Unused Reset phase offset [1] Decr phase offset [0] Incr phase offset Description Resets the incremental phase offset to 0. This is an autoclearing bit. Decrements the incremental phase offset by the amount specified in the incremental phase lock offset step size register (Register 0x0314 to Register 0x0315). This is an autoclearing bit.
PAGE 98
AD9548 Address 0x0A0F 0x0A10 1 Data Sheet Bits [7] Bit Name Ref Mon Override DD [6] Ref Mon Override D [5] Ref Mon Override CC [4] Ref Mon Override C [3] Ref Mon Override BB [2] Ref Mon Override B [1] Ref Mon Override AA [0] Ref Mon Override A [7] [6] [5] [4] [3] [2] [1] [0] Ref Mon Bypass DD Ref Mon Bypass D Ref Mon Bypass CC Ref Mon Bypass C Ref Mon Bypass BB Ref Mon Bypass B Ref Mon Bypass AA Ref Mon Bypass A Description Overrides the reference monitor REF fault signal for Reference
PAGE 99
Data Sheet AD9548 Table 133. SYSCLK Status Address 0x0D01 Bits [7:5] [4] Bit Name Unused Stable [3:2] [1] [0] Unused Cal in progress Lock detected Description The control logic sets this bit when the device considers the system clock to be stable (see the System Clock Stability Timer section). The control logic holds this bit set while the system clock calibration is in progress. Indicates the status of the system clock PLL. 0 = unlocked. 1 = locked (or the PLL is disabled).
PAGE 100
AD9548 Data Sheet Table 138.
PAGE 101
Data Sheet 0x0D0B AD9548 [7] [6] [5:3] Frequency clamped History available Active reference priority [2:0] Active reference The upper or lower frequency tuning word clamp is in effect. There is sufficient tuning word history available for holdover operation. Priority value of the currently active reference. 000 = highest priority. 111 = lowest priority. Index of the currently active reference. 000 = Reference A. 001 = Reference AA. 010 = Reference B. 011 = Reference BB. 100 = Reference C.
PAGE 102
AD9548 Data Sheet NONVOLATILE MEMORY (EEPROM) CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03) Table 142. EEPROM Control Address 0x0E00 0x0E01 0x0E02 0x0E03 Bits [7:2] [1] Bit Name Unused Half rate mode [0] Write enable [7:5] [4:0] Unused Condition value [7:1] [0] Unused Save to EEPROM [7:2] [1] Unused Load from EEPROM [0] Unused Description EEPROM serial communication rate. 0 (default) = 400 kHz (normal). 1 = 200 kHz. EEPROM write enable/protect. 0 (default) = EEPROM write protected.
PAGE 103
Data Sheet AD9548 Table 145. EEPROM Storage Sequence for General Configuration Settings Address 0x0E15 Bits [7:0] Bit Name General Description The default value of this register is 0x14, which the controller interprets as a data instruction. Its decimal value is 20, which tells the controller to transfer 21 bytes of data (20 + 1) beginning at the address specified by the next two bytes. The controller stores 0x14 in the EEPROM and increments the EEPROM address pointer.
PAGE 104
AD9548 Data Sheet Table 148. EEPROM Storage Sequence for Reference Input Settings Address 0x0E1F Bits [7:0] Bit Name Reference inputs 0x0E20 0x0E21 [7:0] [7:0] Reference inputs Description The default value of this register is 0x07, which the controller interprets as a data instruction. Its decimal value is 7, which tells the controller to transfer eight bytes of data (7 + 1) beginning at the address specified by the next two bytes.
PAGE 105
Data Sheet AD9548 Table 151. EEPROM Storage Sequence for Profile 4 and Profile 5 Settings Address 0x0E28 Bits [7:0] Bit Name Profile 4 and Profile 5 Description The default value of this register is 0x63, which the controller interprets as a data instruction. Its decimal value is 99, which this tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and increments the EEPROM address pointer.
PAGE 106
AD9548 Data Sheet Table 154. EEPROM Storage Sequence for End of Data Address 0x0E33 0x0E34 to 0x0E3F Bits [7:0] Bit Name End of data Continuation of user scratch pad area Description The default value of this register is 0xFF, which the controller interprets as an end instruction. The controller stores this instruction in the EEPROM, resets the EEPROM address pointer, and enters an idle state.
PAGE 107
Data Sheet AD9548 POWER SUPPLY PARTITIONS The AD9548 features multiple power supplies, and their power consumption varies with the AD9548 configuration. This section provides information about which power supplies can be grouped together and how the power consumption of each block varies with frequency. The numbers quoted here are for comparison only. Please refer to the Specifications section for exact numbers. With each group, bypass capacitors of 1 μF in parallel with 10 μF should be used.
PAGE 108
AD9548 Data Sheet THERMAL PERFORMANCE Table 156. Thermal Parameters for the AD9548 88-Lead LFCSP Package Symbol θJA θJMA θJMA θJB θJC ΨJT 1 2 Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board 1 Junction-to-ambient thermal resistance, 0.0 m/s airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/s airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
PAGE 109
Data Sheet AD9548 CALCULATING DIGITAL FILTER COEFFICIENTS The digital loop filter coefficients (, , , and  (see Figure 41)) relate to the time constants (T1, T2, and T3) associated with the equivalent analog circuit for a third order loop filter (see Figure 68). Note that AD9548 evaluation software contains a profile designer that will compute these coefficients for you. The user should not normally need to use these formulas.
PAGE 110
AD9548 Data Sheet If x is an integer, then y = x. Otherwise, y is the nearest integer to x. For example, round(2.1) = 2, round(2.5) = 3, and round(−3.1) = −3. The ceil() function where α0, α1, α2, and α3 are the register values. α2 provides front-end gain and α3 provides back-end gain, and α1 shifts the binary decimal point of α0 to the left to accommodate small values of α.
PAGE 111
Data Sheet AD9548 CALCULATION OF THE γ REGISTER VALUES CALCULATION OF THE δ REGISTER VALUES The quantized γ coefficient consists of two components, γ0 and γ1 according to The quantized δ coefficient consists of two components, δ0 and δ1, according to δ ≈ δ quantized = δ 0 × 2 − (15 + δ − γ ≈ γ quantized = γ 0 × 2 − (17 + γ 1 ) where γ0 and γ1 are the register values. Calculation of γ1 is a twostep process that leads to the calculation of γ0, which is also a two-step process.
PAGE 112
AD9548 Data Sheet OUTLINE DIMENSIONS 12.10 12.00 SQ 11.90 0.30 0.23 0.18 0.60 MAX 0.60 MAX 67 66 88 1 PIN 1 INDICATOR PIN 1 INDICATOR 11.85 11.75 SQ 11.65 0.50 BSC 0.50 0.40 0.30 0.85 0.75 23 22 10.50 REF 0.70 0.65 0.60 0.05 MAX 0.01 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VRRD EXCEPT FOR MINIMUM THICKNESS AND LEAD COUNT.