Datasheet

Data Sheet AD9547
Rev. E | Page 93 of 104
STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D19)
All bits in Register 0x0D00 to Register 0x0D19 are read o nl y. These registers are accessible during EEPROM transactions. Register 0x0D00 and
Register 0x0D01 require an IO_UPDATE (Register 0x0005 = 0x01) in order to reflect their latest status.
Table 134. EEPROM Status
Address
Bit
Bit Name
Description
0x0D00
[7:3]
Unused
Unused.
2
Fault detected
An error occurred while saving data to or loading data from the EEPROM.
1 Load in progress The control logic sets this bit while data is being read from the EEPROM.
0
Save in progress
The control logic sets this bit while data is being written to the EEPROM.
Table 135. SYSCLK Status
Address
Bit
Bit Name
Description
0x0D01 [7:5] Unused Unused.
4
Stable
The control logic sets this bit when the device considers the system clock to be
stable (see the System Clock Stability Timer section).
[3:2] Unused Unused.
1 Cal in progress The control logic holds this bit set while the system clock calibration is in progress.
0
Lock detected
Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked (or the PLL is disabled).
Register 0x0D02 to Register 0x0D09—IRQ Monitor
If not masked via the IRQ mask register (Address 0x0209 to Address 0x0210), the appropriate IRQ monitor bit is set to a Logic 1 when the
indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0x0A04 to Address 0x0A0B), the reset all IRQs bit
(Register 0x0A03, Bit 1), or a device reset.
Table 136. IRQ Monitor for SYSCLK
Address
Bit
Bit Name
Description
0x0D02 [7:6] Unused Unused.
5
SYSCLK unlocked
Indicates a SYSCLK PLL state transition from locked to unlocked.
4 SYSCLK locked Indicates a SYSCLK PLL state transition from unlocked to locked.
[3:2]
Unused
Unused.
1 SYSCLK cal complete Indicates that SYSCLK calibration is complete.
0
SYSCLK cal started
Indicates that SYSCLK calibration has begun.
Table 137. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM
Address
Bit
Bit Name
Description
0x0D03
[7:4]
Unused
Unused.
3
Distribution sync
Indicates a distribution sync event.
2 Watchdog timer Indicates expiration of the watchdog timer.
1
EEPROM fault
Indicates a fault during an EEPROM load or save operation.
0 EEPROM complete Indicates successful completion of an EEPROM load or save operation.
Table 138. IRQ Monitor for the Digital PLL
Address
Bit
Bit Name
Description
0x0D04 7 Switching Indicates that the DPLL is switching to a new reference.
6 Closed Indicates that the DPLL has entered closed-loop operation.
5
Free run
Indicates that the DPLL has entered free-run mode.
4 Holdover Indicates that the DPLL has entered holdover mode.
3
Frequency unlocked
Indicates that the DPLL lost frequency lock.
2 Frequency locked Indicates that the DPLL has acquired frequency lock.
1
Phase unlocked
Indicates that the DPLL lost phase lock.
0 Phase locked Indicates that the DPLL has acquired phase lock.