Datasheet

AD9547 Data Sheet
Rev. E | Page 90 of 104
Register 0x0A03—Reset Functions
Table 122. Reset Functions
1
Address
Bit
Bit Name
Description
0x0A03 7 Unused Unused.
6
Clear LF
Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool).
5 Clear CCI Setting this bit (default = 0) clears the CCI filter (intended as a debug tool).
4
Clear phase accumulator
Setting this bit (default = 0) clears DDS phase accumulator (not a recommended action).
3 Reset auto sync Setting this bit (default = 0) resets the automatic synchronization logic (see Register 0x0403).
2
Reset TW history
Setting this bit (default = 0) resets the tuning word history logic (part of holdover
functionality).
1
Reset all IRQs
Setting this bit (default = 0) clears the entire IRQ monitor register (Register 0x0D02 to
Register 0x0D09). It is the equivalent of setting all the bits of the IRQ clearing register
(Register 0x0A04 to Register 0x0A0B).
0
Reset watchdog
Setting this bit (default = 0) resets the watchdog timer (see Register 0x0211 to Register 0x0212).
If the timer times out, it simply starts a new timing cycle. If the timer has not yet timed out,
it restarts at Time 0 without causing a timeout event. Continuously resetting the watchdog timer
at intervals less than its timeout period prevents the watchdog timer from generating a timeout
event.
1
All bits in this register are autoclearing.
Register 0x0A04 to Register 0x0A0B—IRQ Clearing
The IRQ clearing registers are identical in format to the IRQ monitor registers (Address 0x0D02 to Address 0x0D09). When set to Logic 1,
an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ
clearing register is an autoclearing register.
Table 123. IRQ Clearing for SYSCLK
Address
Bit
Bit Name
Description
0x0A04
[7:6]
Unused
Unused.
5 SYSCLK unlocked Clears SYSCLK unlocked IRQ.
4
SYSCLK locked
Clears SYSCLK locked IRQ.
[3:2] Unused Unused.
1
SYSCLK cal complete
Clears SYSCLK calibration complete IRQ.
0 SYSCLK cal started Clears SYSCLK calibration started IRQ.
Table 124. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM
Address Bit Bit Name Description
0x0A05
[7:4]
Unused
Unused.
3
Distribution sync
Clears distribution sync IRQ.
2 Watchdog timer Clears watchdog timer IRQ.
1 EEPROM fault Clears EEPROM fault IRQ.
0
EEPROM complete
Clears EEPROM complete IRQ.
Table 125. IRQ Clearing for the Digital PLL
Address
Bit
Bit Name
Description
0x0A06 7 Switching Clears switching IRQ.
6
Closed
Clears closed IRQ.
5 Free run Clears free-run IRQ.
4
Holdover
Clears holdover IRQ.
3
Frequency unlocked
Clears frequency unlocked IRQ.
2 Frequency locked Clears frequency locked IRQ.
1
Phase unlocked
Clears phase unlocked IRQ.
0
Phase locked
Clears phase locked IRQ.